Dual mode comparator

Abstract

A dual mode comparator circuit is disclosed. The dual mode comparator includes a plurality of differential transistor pairs. Each differential transistor pair includes a plurality of inputs and outputs. The outputs of the differential transistor pairs are coupled to inputs of a multiplexor. The multiplexor includes at least one control input for selecting between the multiplexor inputs and provides the selected input to the multiplexor output. The dual mode comparator further includes a comparator back end that is coupled to the output of the multiplexor. The comparator back end may include a folded cascode and additional gain stages. The comparator back end provides the comparator output to the next stage. The dual mode comparator may be used in automatic testing equipment embodiments.

Description

PRIORITY [0001] The present U.S. patent application claims priority from U.S. Provisional Patent Application No. 60 / 674,580 filed on Apr. 25, 2005 entitled “Dual Mode Comparator” which is incorporated by reference herein in its entirety.TECHNICAL FIELD AND BACKGROUND ART [0002] The present invention relates to comparators and more specifically to dual mode comparators. [0003] It is known in the prior art to have dual mode comparators. Dual mode comparators are often used in automatic testing equipment (ATE) for testing one or more devices under tests (DUTs). Dual mode comparators can operates in any one of a plurality of modes including a differential mode, a common mode, and single-ended mode wherein the mode is selectable based upon an external selection signal provided to the dual mode comparator. The prior art designs provide separate circuitry for each of the modes. Additionally, for each comparison, there is a separate normal windowing comparator (NWC) as shown in FIG. 1. [000...

AI Technical Summary

Benefits of technology

[0005] A dual mode comparator circuit is disclosed. The dual mode comparator includes a plurality of differential transistor pairs. Each differential transistor pair includes a plurality of inputs and outputs. The outputs of the differential transistor pairs are coupled to inputs of a multiplexor. The multiplexor includes at least one control input for selecting between the multiplexor inputs and provides the selected input to the multiplexor output. The dual mode comparator further includes a comparator back end that is coupled to the output of the multiplexor. The comparator back end may include a folded cascode and additional gain stages. The comparator back end provides the comparator output to the next stage. The dual mode comparator may be used in automatic testing equipment embodiments wherein both power and space are at a premium. The disclosed dual mode comparator circuit reduces both the required power and reduces the silicon area need to implement the dual mode comparator as compared with the prior art.

[0008] Also disclosed is a method for selection of an input signal in a dual mode comparator. First, an input signal is compared with another signal (either a reference voltage or another input signal) using a differential transistor pair. The differential transistor pair generates an output based upon the two input signals. A multiplexor is coupled to the output of the differential transistor pair, where a selection signal is received by the multiplexor and the output of the desired differential transistor pair is received by the comparator back end. The comparator back end includes a gain stage that amplifies the desired differential signal. Embodiments of the dual mode comparator reduce the number of gain stages, since a single comparator back end may be shared by a plurality of comparator front ends / differential transistor pairs.

[0009] The dual mode comparator benefits from operating in the current domain, such that the additional capacitance that occurs due to the additional circuitry being coupled to the input node of the front end does not decrease performance.

Problems solved by technology

Therefore, the prior art configuration always requires power for the NWC.

Images