Semiconductor integrated circuit, method of manufacturing semiconductor integrated circuit, charge pump circuit, layout designing apparatus, and layout designing program

Abstract

A layout capable of placing a circuit constituted by a plurality of transistors in a small-with region is automatically formed. A search section inputs data on a circuit and makes a search for a set of routes formed so that passage through any one of the transistors occurs only one time and so that the combination of routes in one set can cover the entire circuit network. An extraction section extracts a set of routes having the smallest number of routes in sets of route found by searching. A width determination section determines the layout width from the widths of source and drain electrodes of each transistor, the width of the region between the source and drain electrodes, the width of the region between some of the adjacent pairs of the transistors not combined into a common electrode, the number of transistors, and the smallest number of routes. A layout determination section forms information on a layout in which all the source, drain and gate electrodes of the transistor included in the circuit are placed in a small-width region having the determined width.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit having transistors formed on a semiconductor substrate, an insulation substrate or a glass substrate and, more particularly, to a semiconductor integrated circuit capable of being laid out in a small-width region and a circuit layout designing method enabling such layout. [0003] 2. Description of the Related Art [0004] For display devices and sensors, a method has generally been used in which peripheral circuits for driving a group of transistors (active matrix) for controlling display elements or sensor elements are mounted around a display region or a sensing region or formed on the same substrate as that for the active matrix (see, for example, patent documents 1 and 2 shown below. To increase the display region or the sensing region, the peripheral circuit is placed in straight narrow regions around the display region or the sensing region. A sm...

AI Technical Summary

Benefits of technology

[0035] According to a twenty-second aspect of the present invention, in the semiconductor integrated circuit according to the nineteenth aspect, at least one of the source and drain electrodes of the transistors to be connected to an external terminal is extended for connection to the external terminal. This arrangement ensures that a semiconductor integrated circuit can be provided which is capable of being connected to external input / output terminals without increasing the layout width even in a case where the external input / output terminals are concentrated on one side so that the degree of design freedom is low.

[0036] According to a twenty-third aspect of the present invention, there is provided a semiconductor integrated circuit according to the sixteenth aspect, the transistors are thin-film transistors formed on a glass substrate or an insulation substrate other than a semiconductor substrate. This arrangement makes it possible to provide a display or a sensor in which a peripheral circuit is mounted in a small-width layout on a display substrate or a sensor substrate with integrated thin-film transistors, and which has an increased display area or an increased sensing region.

[0037] According to a twenty-fourth aspect of the present invention, there is provided a method of manufacturing the semiconductor integrated circuit according to the twenty-third aspect, including advancing crystallization in the gate width direction in a step of crystallizing an amorphous semiconductor layer into a polycrystalline semiconductor. According to this method, the transistors can be crystallized simultaneously with each other and performance variations between the transistors are thereby reduced.

Problems solved by technology

This area is always smaller than the area shown in FIG. 33 if W>0. In this layout, however, a change in layout cannot be made easily because the optimum parallel gate placement varies from transistor to transistor if the complexity of the circuit is increased.

In such circuit layouts, however, the layout area is increased or the transistor-to-transistor layout is complicated and a change in layout cannot be easily made.

Images