Instruction conversion apparatus and instruction conversion method providing power control information, program and circuit for implementing the instruction conversion, and microprocessor for executing the converted instruction
a technology of instruction conversion and instruction, which is applied in the direction of program control, sustainable buildings, instruments, etc., can solve the problems of natural expansion of hardware to a large scale, increase the total power consumption of a microprocessor, and increase the power consumption of the decoding operation. , to achieve the effect of saving power consumption, increasing cycle counts, and reducing processing speed
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embodiment 2
[0068] A second exemplary embodiment of the present invention is described referring to the drawings.
[0069]FIG. 9 shows an instruction conversion apparatus in accordance with the second exemplary embodiment. In FIG. 9, those constituent components identical to those of FIG. 1 are represented by using the same symbols. When an instruction is inserted for the purpose of power control, it increases the code size of a machine language program, which is eventually mounted in a microprocessor. It also increases the instruction execution cycle to impair the processing speed of microprocessor. In some cases, a user may put preference on the code size or the processing speed to the low power consumption. A second embodiment of the present invention addresses the above-described issue; namely, a user is provided with an option to select a level of power control at the time when assembling or compiling is made. A user attaches an option, “−P1” or “-P2”, at the assembling or compiling. The opt...
embodiment 3
[0074] A third exemplary embodiment of the present invention is described referring to the drawings.
[0075]FIG. 10 shows an instruction conversion apparatus in accordance with the third exemplary embodiment. In FIG. 10, those constituent components identical to those of FIG. 1 are represented by using the same symbols. In the first embodiment, a power optimized instruction program 108 is generated by providing an instruction program described by a user with an instruction regarding the power control, by means of insertion or replacing. In the present embodiment, however, an instruction program 101 described by a user is first translated by an instruction translation unit 109 into an object program 1001, which being a row of machine language instruction for execution by a microprocessor. And then, a power optimized object program 110 is generated based on the object program 1001.
[0076] In this case, as shown in FIG. 11, an instruction code is provided with an instruction regarding t...
embodiment 4
[0082] A fourth exemplary embodiment of the present invention is described referring to the drawing.
[0083]FIG. 12 shows the structure of an instruction conversion circuit in accordance with the fourth exemplary embodiment of the present invention. In FIG. 12, an instruction code supply 1200 delivers a non-power optimized object program generated by a conventional method to an instruction storage unit 1205 in a microprocessor. Either a rewritable memory such as a flash memory, or a non-rewritable ROM may be used for the instruction storage unit 1205. The object program was conventionally delivered direct to the instruction storage unit 1205. In the present embodiment 4, however, it is delivered to the instruction storage unit 1205 after going through an instruction conversion circuit 1207 of the present invention and rewritten into a power optimized object program. The instruction conversion circuit 1207 comprises an instruction-wise hardware resource memory 1201, an instruction-wis...
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