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Semiconductor device and method for manufacturing the same

a semiconductor memory and semiconductor technology, applied in the direction of semiconductor memory devices, basic electric elements, electrical appliances, etc., can solve the problems of insufficient examination of the insulating film provided between the control electrodes and the difficulty of obtaining a nonvolatile semiconductor memory devi

Inactive Publication Date: 2007-10-18
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Benefits of technology

[0007]A semiconductor device in accordance with a first aspect of the present invention comprises: a semiconductor substrate; a first insulating film formed on the semiconductor substrate; a charge storage layer formed on the first insulating film; a second insulating film formed on the charge storage layer; and a control electrode formed on the second insulating film, the second insulating film including a lower silico

Problems solved by technology

However, sufficient examinations have not been made for the insulating film provided between the control electrode and the charge storage layer.
It has thus been difficult to obtain a nonvolatile semiconductor memory device offering excellent characteristics and improved reliability.

Method used

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  • Semiconductor device and method for manufacturing the same
  • Semiconductor device and method for manufacturing the same
  • Semiconductor device and method for manufacturing the same

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embodiment 1

[0063]With reference to FIGS. 1A and 1B to 5A and 5B, description will be given of a basic method for manufacturing a semiconductor device (nonvolatile semiconductor memory device) in accordance with the present embodiment. FIGS. 1A to 5A are sectional views in a bit line direction (channel length directions). FIGS. 1B to 5B are sectional views in a word line direction (channel width direction).

[0064]First, as shown in FIGS. 1A and 1B, a tunnel insulating film (first insulating film) 12 of thickness 6 nm is formed on a surface of a silicon substrate (semiconductor substrate) 11 doped with impurities by pyrolysis oxidation. A phosphorus-doped polycrystalline silicon film of thickness 100 nm is subsequently formed by CVD (Chemical Vapor Deposition) as a floating gate electrode film 13. Moreover, a mask film 14 is formed by CVD.

[0065]Then, the mask film 14, polycrystalline silicon film 13, tunnel insulating film 12, and silicon substrate 11 are sequentially etched by RIE (Reactive Ion ...

embodiment 2

[0121]Now, a second embodiment of the present invention will be described. A basic configuration and a basic manufacturing method in accordance with the second embodiment are similar to those in FIGS. 1A and 1B to 5A and 5B for the first embodiment and will not be described in detail. The matters described in the first embodiment will not be described in detail.

[0122]FIG. 13 is a sectional view of a nonvolatile semiconductor memory device in accordance with the present embodiment in the bit line direction (channel length direction). Components corresponding to those shown in FIGS. 1A and 1B to 5A and 5B are denoted by the same reference numerals and will not be described in detail.

[0123]As shown in FIG. 13, the inter-electrode insulating film 20 is formed of a stack film including a lower silicon nitride film 204, a high dielectric constant insulting film (intermediate insulating film) 202 formed on the lower silicon nitride film 204, and an upper silicon nitride film 205 formed on ...

embodiment 3

[0139]Now, a third embodiment of the present invention will be described. A basic configuration and a basic manufacturing method in accordance with the third embodiment are similar to those in FIGS. 1A and 1B to 5A and 5B for the first embodiment and will not be described in detail. The matters described in the first embodiment will not be described in detail.

[0140]FIG. 15 is a sectional view of a nonvolatile semiconductor memory device in accordance with the present embodiment in the bit line direction (channel length direction). Components corresponding to those shown in FIGS. 1A and 1B to 5A and 5B are denoted by the same reference numerals and will not be described in detail.

[0141]As shown in FIG. 15, the inter-electrode insulating film 20 is formed of a stack film including the lower silicon nitride film 204, the lower silicon oxide film 201 formed on the lower silicon nitride film 204, the high dielectric constant insulting film (intermediate insulating film) 202 formed on the...

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Abstract

A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is based upon and claims the benefit of priority from prior Japanese Patent Applications No. 2006-112192, filed Apr. 14, 2006; and No. 2007-037153, filed Feb. 16, 2007, the entire contents of both of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.[0004]2. Description of the Related Art[0005]For nonvolatile semiconductor memory devices, a proposal has been made that a high dielectric constant insulating film be provided between a control electrode and a charge storage layer in order to increase the capacitance between the control electrode and the charge storage layer (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 5-129625).[0006]However, sufficient examinations have not been made for the insulating film provided between the control electrode ...

Claims

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Application Information

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IPC IPC(8): H01L29/76
CPCH01L27/115H01L29/7883H01L29/42324H01L27/11521H10B69/00H10B41/30
Inventor TANAKA, MASAYUKINISHIDA, DAISUKEFUJITSUKA, RYOTASEKINE, KATSUYUKIYAMAMOTO, AKIHITONATORI, KATSUAKIOZAWA, YOSHIO
Owner KK TOSHIBA