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SOI substrate and semiconductor integrated ciruit device
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a technology of integrated circuits and substrates, applied in semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., to achieve the effects of reducing resistance, absorbing noise, and stably operating
Inactive Publication Date: 2007-11-15
RENESAS ELECTRONICS CORP
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Abstract
Description
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Benefits of technology
The present invention provides an SOI substrate and a semiconductor IC device that do not require a dedicated area for reducing noise. The semiconductor region in the substrate has a lower resistivity than the base substrate, and it absorbs noise and prevents malfunctions in the IC. The device can be miniaturized and its stability of operation is improved. Additionally, a guard ring can be included to further absorb noise. The invention also provides methods for forming the semiconductor region and the decoupling capacitor.
Problems solved by technology
Also, a dedicated area for providing the semiconductor region is unnecessary, and thus the device can be miniaturized.
Method used
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first embodiment
[0050] Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, a first embodiment will be described. FIG. 1 is a cross-sectional view showing an SOI substrate 1 according to this embodiment; FIG. 2A is a plan view showing a semiconductor integrated circuit (IC) device 11 according to this embodiment; and FIG. 2B is a cross-sectional view taken along the line A-A in FIG. 2A. In FIG. 2A, side walls 21 and 25, vias 29 and 30, wiring lines 31 and 32, power-supply potential wiring VDD, and ground potential wiring GND, which will be described later, are not shown.
[0051] As shown in FIG. 1, the SOI substrate 1 of this embodiment includes a base substrate 2 comprising P−-type silicon, a P+-type silicon layer 3 is disposed on the entire upper surface of the base substrate 2, and an N+-type silicon layer 4 is disposed on the entire upper surface of the P+-type silicon layer 3. Further, a buried oxide (BOX) layer 5 is disposed on the entire up...
third embodiment
[0079] In the third embodiment, each of the N+-type silicon layer 43 and the P+-type silicon layer 44 is comb-shaped. However, any shape may be adopted as long as a PN junction is formed between the N+-type silicon layer 43 and the P+-type silicon layer 44.
[0080] Further, the via 27 may be omitted, and a ground potential may be applied to the P+-type silicon layer 44 through the base substrate 2, which comprises P−-type silicon. Alternatively, the base substrate 2 may comprise N−-type silicon, and a power-supply potential may be applied to the N+-type silicon layer 43 through the base substrate 2. In this case, the via 26 may be omitted.
[0081] Next, a fourth embodiment of the present invention will be described. FIG. 7 is a cross-sectional view showing a semiconductor IC device 45 according to this embodiment. As shown in FIG. 7, the semiconductor IC device 45 is fabricated by processing the SOI substrate 7 of the third embodiment. Compared to the semiconductor IC device 11 (see FI...
sixth embodiment
[0089] In the semiconductor IC device 48 by applying a power-supply potential to the power-supply potential wiring VDD and by applying a ground potential to the ground potential wiring GND, the decoupling capacitor C6, which is connected in parallel to the power supply, is formed between the N+-type silicon layer 4 and the base substrate 2. Accordingly, the semiconductor IC device 48 can be miniaturized and power noise can be reduced.
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Abstract
A semiconductor IC device includes a base substrate comprising P−-type silicon, a first P+-type silicon layer is provided on the base substrate, and an N+-type silicon layer and a second P+-type silicon layer are provided in the same layer thereon. The impurity concentration of the first P+-type silicon layer and the N+-type silicon layer is higher than that of the base substrate. Also, a buried oxide layer and an SOI layer are provided on the entire upper surface of the N+-type silicon layer and the second P+-type silicon layer. The first P+-type silicon layer is connected to ground potential wiring GND, and the N+-type silicon layer is connected to power-supply potential wiring VDD. Accordingly, a decoupling capacitor, which is connected in parallel to the power supply, is formed between the P+-type silicon layer and the N+-type silicon layer.
Description
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a silicon-on-insulator (SOI) substrate and a semiconductorintegrated circuit (IC) device with reduced noise. In particular, the present invention relates to an SOI substrate and an SOI IC device for realizing larger packing density of elements. [0003] 2. Description of the Related Art [0004] In a hitherto developed SOI technology, a buried oxide (BOX) layer is formed on a silicon substrate, an SOI layer is formed on the BOX layer, and an IC including a MOS transistor or the like is formed in the SOI layer. With this technology, a MOS transistor can be driven at high speed (for example, Patent Document 1: Japanese Unexamined Patent Application Publication No. 2001-339071). [0005] Recently, however, an operating frequency of semiconductorIC devices has been extremely high and a greater area has been allocated for power-supply wiring and ground wiring. When a semiconductor IC device i...
Claims
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Application Information
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Patent Type & Authority Applications(United States)
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