Method and apparatus for dedicated hardware and software split implementation of rate matching and de-matching

a technology of dedicated hardware and software, applied in the direction of forward error control, electrical equipment, transmission, etc., can solve problems such as excessive load, achieve the effects of reducing the total processing load, eliminating processor cycles, and processing data much more efficiently

Inactive Publication Date: 2007-11-15
BARRY MARK P +2
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach significantly reduces processor cycles associated with puncturing and repetition, resulting in a more economical and faster implementation of rate matching and rate de-matching, enhancing overall system efficiency.

Problems solved by technology

Unfortunately, a general purpose processor running software to perform rate-matching (e.g., a programmed digital signal processor (DSP)) requires in the order of 60 instruction cycles per bit of processed data to perform the puncturing and repetition process.
The processor load required for processing 64 users is in the order of 240 million cycles per second which is an excessive load.

Method used

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  • Method and apparatus for dedicated hardware and software split implementation of rate matching and de-matching
  • Method and apparatus for dedicated hardware and software split implementation of rate matching and de-matching
  • Method and apparatus for dedicated hardware and software split implementation of rate matching and de-matching

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first embodiment

of Downlink Rate Matching Dedicated Hardware Architecture

[0030]FIG. 2 illustrates a block diagram of the dedicated hardware architecture for rate matching according to one embodiment of the present invention, wherein the embodiment is employed between an encoder and an interleaver. As shown, on the input side, the dedicated hardware 6 receives the rate-matching parameters from the DSP 4, and receives input data data_in from an encoder 20. For the purposes of explanation only, four types of data (non-Turbo data, Systematic data, Parity 1 data and Parity 2 data) will be described in detail below. The dedicated hardware 6 also supplies the encoder 20 with a stall signal stall_out. On the output side, the dedicated hardware 6 outputs data data_out to, for example, an interleaver 22. The dedicated hardware 6 also outputs an output validity indicator valid_out.

[0031] The dedicated hardware 6 includes a first data register 34 storing the input data data_in, a second data register 36 stori...

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Abstract

In the method of rate-matching, software is used to calculate at least one rate-matching parameter for data, and dedicated hardware is used to perform at least one of a puncturing and repetition process on data based on the calculated rate-matching parameter. In rate de-matching, software is again used to calculate at least one rate de-matching parameter for received data, and dedicated hardware is used to compensate for puncturing and repetition based on the calculated rate de-matching parameter.

Description

[0001] This is a continuation of, and claims priority under 35 U.S.C. ยง121 on, U.S. application Ser. No. 10 / 425,825, filed Apr. 30, 2003, the entire contents of which is incorporated herein by reference.BACKGROUND OF INVENTION [0002] Rate-matching is a technique widely used in 3G wireless communication systems, such as UMTS and CDMA2000, for adjusting the data size of the channel encoder outputs at the transmitter to the air interface capacity. Rate-matching applies puncturing or repetition to each channel's data based on well-known calculated rate-matching parameters. Within a channel, a puncture or repetition pattern is applied. A reverse process called rate de-matching is performed by the receiver side to restore the punctured / repeated data. [0003] The conventional implementation of rate-matching and rate de-matching is to use software to do both parameter calculation and data processing (i.e., puncture and repetition as dictated by the parameter calculation). As used herein, sof...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H03M13/03H03M13/00H04L1/00H04L1/08
CPCH04L1/0043H04L1/0045H04L1/0059H04L1/0067H04L1/0069H04L1/0071H04L1/08H04L1/0066
InventorBARRY, MARK P.LI, YI-CHEN J.RIDLER, OLIVER J.
OwnerBARRY MARK P