Tail-current steering circuit and method for rail-to-rail operational amplifier input stage

Abstract

An amplifier includes first and second pairs of differentially coupled input transistors. The first current mirror generates a reference current which is mirrored by a second current mirror to produce a mirrored reference current. Current steering circuitry steers the mirrored reference current as a first tail current through the first pair when a common mode voltage associated with a differential input voltage exceeds a first reference voltage. A first portion of the mirrored reference current flows from the first current steering circuitry when the common mode voltage is greater than the first reference voltage to produce a second tail current for the second pair. A second portion of the mirrored reference current is fed back to an output of the first current mirror and summed with the reference current so as to reduce the second portion when the common mode voltage is greater than the first reference voltage.

Description

BACKGROUND OF THE INVENTION[0001]The present invention relates generally to rail-to-rail operational amplifiers, and more particularly to improved circuitry for avoiding excess bias current in circuitry which generates tail currents for opposite-conductivity pairs of differentially coupled input transistors when the common mode input voltage is at a high level.[0002]U.S. Pat. No. 5,311,145, issued May 10, 1984 entitled “Combination Driver-Summing Circuit for Rail-to-Rail Differential Amplifier” by Huijsing et al. is believed to be generally indicative of the closest prior art. A “rail-to-rail” operational amplifier is one which has the capability of operating with its common mode input voltage having a value anywhere between the upper and lower power supply voltage rails. In order to achieve a rail-to-rail common-mode input voltage range of an operational amplifier without the use of a charge pump, two pairs of opposite-conductivity inserted after noise input transistors are needed,...

AI Technical Summary

Benefits of technology

[0009]It is an object of the invention to provide rail-to-rail differential input amplifier circuitry which avoids wasting bias current when a particular pair of differentially coupled input transistors is turned off.

[0010]It is another object of the invention to provide rail-to-rail operational amplifier circuitry which avoids wasting bias current when a particular pair of differentially coupled input transistors is turned off in the case wherein the operational amplifier circuitry is being designed for a low noise-to-current ratio.

[0018]In one embodiment, the invention provides a method of reducing waste bias current in amplifier circuitry which includes a first pair of differentially coupled input transistors (Q1,Q2), a differential input voltage (Vin+−Vin−) being coupled between gates of the first pair, and a second pair of differentially coupled input transistors (Q3,Q4), the differential input signal also being coupled between gates of the second pair, drains of the first and second pairs of differentially coupled input transistors being coupled to a folded-cascode stage (3), first current mirror circuitry (I3,Q6,Q8) for generating a reference current (IR), second current mirror circuitry (Q9,Q12) receiving the reference current (IR) and producing a mirrored reference current (IP), and first current steering circuitry operative to steer the mirrored reference current (IP) as a first tail current (I1) through the first pair of differentially coupled input transistors (Q1,Q2) when a common mode voltage (VCM) associated with the differential input voltage (Vin+−Vin−) exceeds a first reference voltage (Vref2), wherein the method includes amplifying a first portion (IP′) of the mirrored reference current (IP) when the common mode voltage (VCM) is greater than the first reference voltage (Vref2) to produce a second tail current (I22) for the second differentially coupled pair of transistors (Q3,Q4), feeding a second portion (IF) of the mirrored reference current (IP) back to an output of the first current mirror (I3,Q6,Q8) and summing the second portion (IF) of the mirrored reference current (IP) with the reference current (IR) so as to reduce the first portion (IP′) of the mirrored reference current (IP) when the common mode voltage (VCM) is greater than the first reference voltage (Vref2). In one embodiment, the method includes providing a W / L ratio (channel-width-to-channel-length ratio) of the first current mirror output transistor (Q12) equal to a ratio N times a W / L ratio of the first current mirror control transistor (Q9) and also providing a W / L ratio of the first current steering transistor (Q14) equal to a ratio M times a W / L ratio of the second current steering transistor (Q17), wherein the third current mirror circuitry (Q15,Q16,Q11,Q10) includes a N-channel second current mirror control transistor (Q16) and a N-channel second current mirror output transistor (Q11). A W / L ratio (channel-width-to-channel-length ratio) of the second current mirror output transistor (Q11) is provided to be equal to 1+(N+1) / M times a W / L ratio of the second current mirror control transistor (Q16) so as to cause the second tail current (I2) to have the same value when the common mode voltage (VCM) is greater than the first reference voltage (Vref2) that the first tail current (I1) has when the common mode voltage (VCM) is less than the first reference voltage (Vref2).

Problems solved by technology

Although the technique for generating tail current in FIG. 1 is very common, it is wasteful of current (and power).

However, if the circuit of FIG. 1 is designed to optimize the noise-to-current ratio (or noise-to-power ratio), then there typically will be relatively large input tail currents, which would result in very fast amplifier operation, making it necessary to use frequency compensation techniques to reduce the speed to a normal level, since the only way to reduce the total quiescent current of the operational amplifier is to reduce the speed.

That is, if the circuit of FIG. 1 is being designed to minimize the noise for a given total quiescent current, the tail current typically will be a much more significant portion of the total quiescent current for the operational amplifier, and the large value of IP that is required to generate the large value of N-channel tail current I2 becomes problematic.

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