Planarization polishing method and method for manufacturing semiconductor device

a technology for semiconductor devices and polishing methods, which is applied in the direction of manufacturing tools, threaded fasteners, lapping machines, etc., can solve the problems of ceria-based slurry causing more scratches, deteriorating yield, and becoming difficult to obtain a polished surface with high planarity

Inactive Publication Date: 2008-08-14
SONY CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0020]In these methods, the surfactant contained in the polishing slurry is encapsulated through coating of its surface. Therefore, the surfactant is selectively supplied only to a small-height region that should be protected by the surfactant through the breaking of the capsules. In contrast, in the other region, the capsules are not broken, so that no protection effect is provided and thus the polishing proceeds. This feature allows high-planarization polishing.

Problems solved by technology

However, even for the STI-CMP process employing ceria-based slurry, it is becoming difficult to obtain a polished surface with high planarity due to the influence of difference in the density of the element formation region.
Moreover, the ceria-based slurry has also a problem of causing more scratches compared with silica-based slurry.
In particular, if scratches are generated in an element formation region and reach the underlying Si substrate, the yield is problematically deteriorated.

Method used

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  • Planarization polishing method and method for manufacturing semiconductor device
  • Planarization polishing method and method for manufacturing semiconductor device
  • Planarization polishing method and method for manufacturing semiconductor device

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Embodiment Construction

[0030]Embodiments of the present invention will be described below with reference to the drawings. It should be noted that embodiments of the present invention are not limited to the following exemplification.

[0031]In the following description, the embodiments are applied to manufacturing of a semiconductor device, specifically, a so-called semiconductor integrated circuit, and particularly to planarization polishing of an oxide film by CMP for formation of element isolation regions based on STI for the semiconductor integrated circuit. In the embodiments, the polishing-target film is a high-density plasma SiO2 film as one example.

[0032]FIG. 1 shows the schematic structure of general CMP apparatus used for the polishing of the embodiments. This CMP apparatus 21 has a platen 23 that is disposed rotatably around a rotation shaft 22, and a polishing pad 24 is disposed on the platen 23. Above the polishing pad 24, a slurry feed pipe 26 for supplying polishing slurry 25 according to the ...

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Abstract

Disclosed herein is a planarization polishing method for polishing a polishing-target wafer for a planarized surface, the method including the step of polishing a polishing-target surface into a planarized surface by using polishing slurry that contains an abrasive grain and a surfactant encapsulated through surface coating.

Description

CROSS REFERENCES TO RELATED APPLICATIONS[0001]The present invention contains subject matter related to Japanese Patent Application JP 2007-029798 filed in the Japan Patent Office on Feb. 8, 2007, the entire contents of which being incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a planarization polishing method used in a semiconductor manufacturing process and a method for manufacturing a semiconductor device.[0004]2. Description of the Related Art[0005]In a manufacturing process for a semiconductor device, i.e., a so-called semiconductor integrated circuit, a chemical mechanical polishing (CMP) technique is widely used as a technique for surface planarization in a step for forming shallow trench isolation (STI) regions serving as element isolation regions of the semiconductor integrated circuit. In general, STI regions in a semiconductor device are formed in the manner shown in FIG. 6.[0006]Initially, ...

Claims

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Application Information

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IPC IPC(8): B24B1/00B24B37/00H01L21/304
CPCB24B37/044H01L21/31053C09G1/02H02G3/0456F16B17/006H02G3/0406H02G3/30F16B37/04
InventorFUJII, MIKA
OwnerSONY CORP