Method for manufacturing semiconductor package

Abstract

A method for manufacturing a semiconductor package includes forming a groove in the portion outside of the bonding pad of a semiconductor chip provided with the bonding pad on an upper surface thereof; forming an insulation layer on the side wall of the groove; forming a metal layer over the semiconductor chip so as to fill the groove formed with the insulation layer; etching the metal layer to simultaneously form a through silicon via for filling the groove and a distribution layer for connecting the through silicon via and the bonding pad; and removing a rear surface of the semiconductor chip such that the lower surface of the through silicon via protrudes from the semiconductor chip.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application claims priority to Korean patent application number 10-2007-0060263 filed on Jun. 20, 2007, which is incorporated herein by reference in its entirety.BACKGROUND OF THE INVENTION[0002]The present invention relates to a method for manufacturing a semiconductor package, and more particularly to a method for manufacturing a semiconductor package, which is capable of simplifying a process and reducing a manufacturing cost.[0003]Packaging technologies for a semiconductor integrated device have been continuously developed to satisfy the demands for miniaturization and high capacity. Recently, various technologies for a stack type semiconductor package, which is capable of satisfying the demands for mounting efficiency as well as miniaturization and high capacity, have been developed.[0004]The term “stack” in the semiconductor industry refers to a technology in which at least two semiconductor chips or packages are stacked...

AI Technical Summary

Benefits of technology

[0016]Embodiments of the present invention are directed to a method for manufacturing a semiconductor package which is capable of simplifying the process and reducing manufacturing costs.

Problems solved by technology

However, in the conventional stack type semiconductor package using metal wires, since an electrical signal exchange is transmitted through the metal wire, the high number of wires used results in a low speed and a deterioration in electrical properties.

Further, the formation of the metal wires necessitates an additional area on the substrate thereby increasing the size of the package and the space required between the semiconductor chips for bonding the metal wires increases the height of the package.

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