Semiconductor apparatus and method for manufacturing the same

Abstract

A semiconductor apparatus including a semiconductor substrate, an insulating layer, a via hole, and a through-hole interconnection is provided. The insulating layer is formed on the semiconductor substrate. The via hole is formed through the semiconductor substrate and the insulating layer. The through-hole interconnection has a conductive layer formed on an insulating layer in the via hole. The surface of the insulating layer formed on the inner surface of the via hole is substantially planarized by filling a recessed portion on a boundary between the semiconductor substrate and the insulating layer formed on the semiconductor substrate.

Description

CROSS REFERENCES TO RELATED APPLICATIONS[0001]The present invention contains subject matter related to Japanese Patent Application JP 2008-002553 filed in the Japanese Patent Office on Jan. 9, 2008, the entire contents of which being incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a semiconductor apparatus with a through-hole interconnection formed in a semiconductor chip and a method for manufacturing the same.[0004]2. Description of the Related Art[0005]Heretofore, attention has been given to CSP (chip size package or chip scale package) structure as the miniaturized or thinned structures of semiconductor devices, such as LSIs.[0006]Many of CSPs are provided as ball grid arrays (BGAs) in which balls such as those made of solder are arranged on the uppermost surface of an apparatus or land grid array (LGAs) in which a plurality of flat electrodes are arranged.[0007]In addition, in the case of the CSP ...

AI Technical Summary

Benefits of technology

[0046]Furthermore, when the pad electrode 202 is exposed by etching back the insulating layer 204 formed on the inner surface of the via hole 218, the insulating layer 204 on a portion 220 with a gentle slope angle of the inner surface of the vial hole 218 is excessively etched compared to other portions. Therefore, at the portion 220 with a gentle slope angle of the inner surface, the thickness of the insulating layer 204 becomes small or the insulating layer 204 may be completely removed, thereby exposing semiconductor substrate 210. Therefore, in the semiconductor apparatus, the insulation properties of both the semiconductor substrate 210 and the conductive layer 205 may be reduced, causing a decrease in electric characteristics and a decrease in reliability of the semiconductor apparatus.

[0055]According to the embodiments of the semiconductor apparatus and the method for manufacturing the semiconductor apparatus of the present invention, the through-hole interconnection is configured such that the inner surface of the via hole is allowed to be planarized by filling the recessed portion formed in the semiconductor substrate with the insulating layer. Subsequently, the conductive layer is formed on the planarized insulating layer. Thus, when the via hole is formed, the conductive layer is formed on the planarized surface without being affected by the recessed portion formed on the boundary between the semiconductor substrate and the insulating layer on the inner surface of the via hole, and the through-hole interconnection can be formed. Therefore, the reliability of the semiconductor apparatus can be improved, because the conductive layer is prevented from forming a portion, such as a convex portion, where the stress of thermal expansion due to thermal history or the like may be concentrated.

[0056]According to an embodiment of the present invention, a highly reliable semiconductor apparatus with a through-hole interconnection can be obtained.

Problems solved by technology

Therefore, a wiring line may not be formed stably by electrolytic plating because of disconnection of the seed metal or undesirable characteristics of the recessed portion 215.

As a result, malfunction of the semiconductor apparatus may occur.

As described above, the recessed portion existing on the boundary between the semiconductor chip and the wiring layer causes a decrease in yield when manufacturing a semiconductor apparatus and a decrease in reliability thereof.

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