Unlock instant, AI-driven research and patent intelligence for your innovation.

Semiconductor device, rf-ic and manufacturing method of the same

a technology of semiconductor devices and semiconductors, applied in the direction of fixed capacitors, pulse generators, pulse techniques, etc., can solve the problems of substantially difficult inability to use intermediate electrodes as general interconnects, and inability to so as to reduce the space occupied by capacitors and reduce the parasitic capacitance of capacitors

Inactive Publication Date: 2010-01-21
RENESAS ELECTRONICS CORP
View PDF16 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0008]An object of the present invention is to provide a technology capable of reducing the parasitic capacitance of a capacitor while reducing the space occupied by the capacitor.
[0015]The present invention makes it possible to decrease the parasitic capacitance of a capacitor while reducing the space occupied by the capacitor by stacking plural capacitors one after another and at the same time, by equipping an electrode constituting each capacitor with a portion not in direct contact with a capacitor insulating film.

Problems solved by technology

Hei 10(1998)-326863, the parasitic capacitance due to the intermediate electrode becomes equal to that of the first capacitor so that use of it as a general interconnect inevitably increases signal delay or power consumption.
This makes it substantially difficult to use the intermediate electrode as general interconnects.
In particular, in a circuit operating at high frequencies requires high-speed operation so the intermediate electrode cannot be used as a general interconnect without reducing the parasitic capacitance between interconnects.
Increase in signal delay or power consumption therefore occurs in the electrode using a polysilicon film compared with that using a metal film.
This makes it difficult to use the electrode using a polysilicon film as a general interconnect.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor device, rf-ic and manufacturing method of the same
  • Semiconductor device, rf-ic and manufacturing method of the same
  • Semiconductor device, rf-ic and manufacturing method of the same

Examples

Experimental program
Comparison scheme
Effect test

embodiment 1

[0061]FIG. 1 is a cross-sectional view illustrating a portion of a semiconductor device of Embodiment 1. As illustrated in FIG. 1, an n channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) 2 and a p channel MISFET 3 are formed over a semiconductor substrate 1 made of silicon single crystal. In a region other than the formation regions of the n channel MISFET 2 and p channel MISFET 3, a capacitor 4 having an MIM structure is formed. In short, MISFETs and capacitor are formed over the semiconductor substrate 1. In the drawings after FIG. 1, MISFETs formed over the semiconductor substrate 1 are omitted and only a capacitor formed over an interlayer insulating film is illustrated.

[0062]FIG. 2 is a plan view of the capacitor 4 viewed from above. In FIG. 2, a lower electrode (first electrode) 10 is formed in the capacitor 4 and it has an intermediate electrode (second electrode) 11 formed thereover via an insulating film (not illustrated). In a region where the lower ele...

embodiment 2

[0094]In Embodiment 1, the intermediate interconnect 39 connected to an upper-level interconnect was described. In Embodiment 2, on the other hand, a manufacturing method of an interconnect 39 connected not only to an upper-level interconnect but also to a lower-level interconnect will be described referring to accompanying drawings.

[0095]As illustrated in FIG. 13, a titanium nitride film 31a, aluminum film 31b and titanium nitride film 31c are successively stacked over an insulating film 30. The titanium nitride film 31a, aluminum film 31b and titanium nitride film 31c can be formed using, for example, sputtering. By photolithography and etching, the titanium nitride film 31a, aluminum film 31b and titanium nitride film 31c are patterned to form a lower electrode (first electrode) 32 and a lower-level interconnect 53 each composed of the titanium nitride film 31a, aluminum film 31b and titanium nitride film 31c. An insulating film (first insulating film) 33 is then formed over the ...

embodiment 3

[0106]In this Embodiment 3, an example of forming a variable capacitor having a stacked structure will be explained. FIG. 22 is a plain view illustrating the capacitor of Embodiment 3. In FIG. 22, a lower electrode 10 is formed and this lower electrode 10 has an intermediate electrode 11 formed thereover via an insulating film (not illustrated). In a region where the lower electrode 10 and intermediate electrode 11 two-dimensionally overlap each other, a capacitor Ca is formed. Over the intermediate electrode 11, upper electrodes 12a to 12c and an interconnect 13 are formed via an insulating film (not illustrated). In a region where the intermediate 11 and upper electrode 12a two-dimensionally overlap each other, a capacitor Cb is formed, while in a region where the intermediate 11 and upper electrode 12b two-dimensionally overlap each other, a capacitor Cc is formed. In a region where the intermediate 11 and upper electrode 12c two-dimensionally overlap each other, a capacitor Cd i...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]The present application is a continuation of U.S. patent application Ser. No. 11 / 473,229, filed Jun. 23, 2006 which claims priority from Japanese patent application No. 2005-186967 filed on Jun. 27, 2005, the content of which is hereby incorporated by reference into this application.BACKGROUND OF THE INVENTION[0002]The present invention relates to a semiconductor device, a transmitter-receiver device using it, and a manufacturing method of the semiconductor device, particularly to, a technology effective when applied to a semiconductor device requiring a reduction in the space occupied by a capacitor formed on a semiconductor chip.[0003]A technology of reducing the space of a capacitor while maintaining adequate capacitance by changing the MIM (Metal Insulator Metal) structure of the capacitor to a stacked structure is disclosed (refer to, for example, Japanese Unexamined Patent Publication No. 2004-200640 and Japanese Unexamined Patent Pu...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(United States)
IPC IPC(8): H03B5/18H01G4/00H03H7/38H03H7/00
CPCH01L27/10852H01L28/91H01L28/87H10B12/033
Inventor FUJIWARA, TSUYOSHIIMAI, TOSHINORISAIKAWA, TAKESHIKAWASAKI, YOSHIHIROTOYA, MITSUHIROMORI, SHUNJIOKABE, YOSHIYUKI
Owner RENESAS ELECTRONICS CORP