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Video processing ciucuit and related method for merging video output streams with graphical stream for transmission

a video processing circuit and video output stream technology, applied in the field of video processing circuits, can solve the problems of /o pins are needed, and poor quality around the edges of the graphic data dsub>1 /sub>area, etc., and achieve the effect of reducing the number of pins assigned

Inactive Publication Date: 2010-05-27
MEDIATEK INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0007]It is one of the objectives of the claimed disclosure to provide a video processing circuit and related method for merging video output streams with a graphical stream for transmission, thereby reducing the number of pins assigned for transmitting the main video data (e.g., display data) and the auxiliary video data (e.g., OSD data).
[0009]In one embodiment, the communication interface circuit merges the video output stream and the graphical stream by increasing a working frequency of the communication interface circuit to increase a bandwidth of the channel, by using positions for transmitting a portion of video control signals in the video output stream to transmit the graphical stream, and by compressing the video output stream.

Problems solved by technology

Thus the quality around edges of the graphic data D1 area may be poor as the video enhancement is applied to the mixed data DMIX including contents of the graphic data D1 which replace an overlapped portion within the contents originally carried by the video output stream SOUT and are far different from remaining contents corresponding to the video output stream SOUT.
However, if the video output stream SOUT and the graphic data D1 are mixed during the operation of the video processing chip, both the video output stream SOUT and the graphic data D1 are post-processed by the video post-processing chip, resulting in a poor quality around the graphic data D1 area as the mixing process occurs prior to the post-processing process.
The disadvantage of this case is that extra I / O pins are needed to transmit the graphic data D1, which is not economical for cost.

Method used

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  • Video processing ciucuit and related method for merging video output streams with graphical stream for transmission
  • Video processing ciucuit and related method for merging video output streams with graphical stream for transmission
  • Video processing ciucuit and related method for merging video output streams with graphical stream for transmission

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Experimental program
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first embodiment

[0035]Please refer to FIG. 4. FIG. 4 is a diagram of a video processing circuit 400 according to the present disclosure. The video processing circuit 400 includes, but not limited to, a video processing chip 410, a video post-processing chip 420, and a video output device 430. In one embodiment, a video generating unit 412, a graphic generating unit 414, and a communication interface circuit 416 are disposed in the video processing chip 410; and a first signal receiver 422, a video post-processing unit 424, a decoding unit 426, a mixer 428, and a second signal transmitter 429 are disposed in the post-processing chip 420 coupled to the video processing chip 410.

[0036]Please continue referring to FIG. 4. The video generating unit 412 is utilized for generating a video output stream SOUT according to a video input stream SIN, and the graphic generating unit 414 is utilized for providing a graphical stream PD1. The communication interface circuit 416 is coupled to the video generating u...

second embodiment

[0042]Please refer to FIG. 5. FIG. 5 is a diagram of a video processing circuit 500 according to the present disclosure. In FIG. 5, elements with the same reference numerals as that in FIG. 4 refer to the same elements, further detailed description is omitted herein. In this embodiment, the graphic generating unit is an OSD encoder 514 and is disposed in a video processing chip 510, and the decoding unit is an OSD decoder 526 disposed in a video post-processing chip 520. In this embodiment, the communication interface circuit 416 is in the second mode. The OSD encoder 514 generates the graphical stream PD1 (that is to say an OSD data herein), and the communication interface circuit 416 then merges the video output stream SOUT and the graphical stream PD1 (i.e., the OSD data) to generate a first merged signal SM1. After the first signal receiver 422 receives the first merged signal SM1 and extracts the video output stream SOUT and the graphical stream PD1 (the OSD data) from the firs...

third embodiment

[0043]FIG. 6 is a diagram of a video processing circuit 600 according to the present disclosure. In FIG. 5, elements with the same reference numerals as that in FIG. 4 refer to the same elements, further detailed description is omitted herein. In this embodiment, the graphic generating unit is an external storage device 614 of a video processing chip 610, and a video post-processing chip 620 further includes a second storage device 625 coupled to the decoding unit 426. Please note that, the external storage device 614 is not disposed in the video processing chip 610, and acts as an external data source for storing and providing the graphical stream PD1. In this case, the graphical stream PD1 can be a table, an index, a program code, or other data used in certain video applications, but this is for illustrative purpose only and is not meant to be a limitation of the present disclosure. In this embodiment, the communication interface circuit 416 is in the second mode. The external sto...

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PUM

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Abstract

A video processing circuit includes a video generating unit for generating a video output stream, a graphic generating unit for providing a graphical stream, and a communication interface circuit coupled to the video generating unit and the graphic generating unit. The communication interface circuit has a first mode provided for mixing the video output stream and the graphical stream to transmit a mixed video output stream through a channel and a second mode provided for merging the video output stream and the graphical stream to transmit a first merged signal through the channel. In the second mode, the communication interface circuit merges the video output stream and the graphical stream by increasing a working frequency of the communication interface circuit to increase bandwidths of the channel, using positions for transmitting a portion of video control signals in the video output stream to transmit the graphical stream, and compressing the video output stream.

Description

BACKGROUND[0001]The present disclosure relates to a video processing circuit and related method thereof, and more particularly, to a processing circuit and related method for merging video output streams with a graphical stream for transmission.[0002]In a typical digital TV chip application, auxiliary graphics, e.g. on screen display (OSD) information, are usually overlaid on video output streams as user interfaces or user menus. Generally, the graphics and the video output streams are mixed into a single mixed data by a conventional mixer, and the mixed data is then transmitted to a display panel for further display. Please refer to FIG. 1. FIG. 1 is a diagram of a first conventional video processing circuit 100. The video processing circuit 100 includes a video processing chip 110 and a video output device 130, whereof the video processing chip 110 includes a video generating unit 112, an OSD encoder 114, a mixer 116, and a first signal transmitter 118. The generating unit 112 is ...

Claims

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Application Information

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IPC IPC(8): H04N11/02
CPCH04N5/44508H04N21/431H04N7/0806H04N5/265H04N21/44016H04N21/434
Inventor SHIH, YANG-HUNGLIN, HUNG-DERPO, TANG-HUNGCHIU, SAU-KWO
Owner MEDIATEK INC