Method of Fabricating Non-volatile Memory Device

a memory device and non-volatile technology, applied in the direction of semiconductor devices, basic electric elements, electrical appliances, etc., can solve the problems of deteriorating leakage current properties, difficult to actually apply the intergate insulation layer, and difficult to reduce the thickness of an effective oxide layer, so as to prevent the deterioration of leakage current

Inactive Publication Date: 2011-01-20
SK HYNIX INC
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach effectively prevents leakage current deterioration while maintaining a sufficiently thin high-k dielectric layer, enhancing the integration density and reliability of non-volatile memory devices.

Problems solved by technology

However, it is known that it is not easy to reduce the thickness of an effective oxide layer to below a certain thickness with the currently used intergate insulation layer 130 with the ONO structure.
For example, in order to maintain a coupling ratio above 0.5 while employing the planar structure, the thickness of the effective oxide layer should be maintained below 80 Å. However, it is hard to actually apply the intergate insulation layer 130 of the ONO structure having the thickness of the effective oxide layer of below 80 Å since leakage current is rapidly increased.
However, the use of the high-k dielectric layer as the intergate insulation layer 130 may cause the following problems.
Second, crystallization of the high-k dielectric layer itself by the subsequent thermal process occurs and this may deteriorate the leakage current properties.
Third, phase separation of the high-k dielectric layer by the subsequent thermal process occurs and impurities are diffused into the high-k dielectric layer upon formation of the control gate layer electrode 140, which may lead to deterioration of the leakage current properties.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method of Fabricating Non-volatile Memory Device
  • Method of Fabricating Non-volatile Memory Device
  • Method of Fabricating Non-volatile Memory Device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0023]Hereinafter, preferred embodiments of the present invention will be described with reference to accompanying drawings. The embodiments are for illustrative purposes only, and the scope of the present invention is not limited thereto.

[0024]FIGS. 2 to 7 are cross-sectional views illustrating a method of fabricating a non-volatile memory device in accordance with an embodiment of the present invention. Referring first to FIG. 2, a tunnel insulation layer 212 is formed over a semiconductor substrate 200. The tunnel insulation layer 212 may be formed of an oxide layer. Next, a floating gate electrode layer 222 is formed over the tunnel insulation layer 212. The floating gate electrode layer 222 may be formed of a polysilicon layer but not limited thereto. When the floating gate electrode layer 222 is formed of a polysilicon layer, the polysilicon layer may have been doped with phosphorous at a doping concentration of about 5×1019 to 3×1020 / cm3.

[0025]Referring next to FIG. 3, patter...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A method of fabricating a non-volatile memory device includes: forming a tunnel insulation layer pattern and a floating gate electrode layer pattern over a semiconductor substrate; forming an isolation trench by etching an exposed portion of the semiconductor substrate so that the isolation trench is aligned with the tunnel insulation layer pattern and the floating gate electrode layer pattern; forming an isolation layer by filling the isolation trench with a filling insulation layer; forming a hafnium-rich hafnium silicon oxide layer over the isolation layer and the floating gate electrode layer pattern; forming a hafnium-rich hafnium silicon oxynitride layer by carrying out a first nitridation on the hafnium-rich hafnium silicon oxide layer; forming a silicon-rich hafnium silicon oxide layer over the hafnium-rich hafnium silicon oxynitride layer; forming a silicon-rich hafnium silicon oxynitride layer by carrying out a second nitridation on the silicon-rich hafnium silicon oxide layer; and forming a control gate electrode layer over the silicon-rich hafnium silicon oxynitride layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This is a division of U.S. application Ser. No. 12 / 345,785 filed Dec. 30, 2008, which claims the priority benefit under USC 119 of KR 10-2008-0032272 filed Apr. 7, 2008, the entire respective disclosures of which are incorporated herein by reference.[0002]The present invention relates to a method of fabricating a non-volatile memory device, and more particularly, to a method of fabricating a non-volatile memory device which employs a high-k dielectric layer as an intergate insulation layer.[0003]Memory devices used to store data may be classified into a volatile memory device and a non-volatile memory device depending on ability whether it can maintain the data even when power supply is cut off. While the volatile memory device loses the stored data when the power supply is cut off, the non-volatile memory device maintains the stored data even when the power supply is cut off. Therefore, the non-volatile memory device is widely used where...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L21/336H10B69/00
CPCH01L21/28273H01L21/3145H01L21/31645H01L29/7881H01L29/513H01L29/518H01L21/76224H01L29/40114H01L21/02263H01L21/02181H01L21/28202H01L29/42324H01L29/66825H10B41/30
InventorJOO, MOON SIGCHO, HEUNG JAEKIM, YONG SOOCHOI, WON JOON
OwnerSK HYNIX INC