Method for packaging wafer

Abstract

A method for packaging a wafer is provided, which includes: providing a bare wafer; forming a plurality of through silicon vias across through the bare wafer, the through silicon vias being filled with a conducting metal; forming a redistribution layer on the bare wafer, the redistribution layer being connected to each of the through silicon vias; performing a chemical mechanical polishing process to planarize a surface of the bare wafer; performing a wafer forming process to treat the planarized bare wafer; forming a metal layer on the wafer after processed; forming a plurality of connection pads on the metal layer, the connection pads being respectively electrically connected to their corresponding through silicon vias; forming a passivation layer on the metal layer; and forming a plurality of solder balls or metal bumps on a backside surface of the wafer through which the processed wafer is electrically connected to a substrate.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a method for packaging a wafer, and more particularly to a method for packaging a wafer in which the through silicon vias (TSV) and the redistribution layer (RDL) are formed on a bare wafer before the semiconductor circuits are formed thereon.[0003]2. The Prior Arts[0004]In a conventional method for packaging a wafer level package, the wafer is packaged after the circuits have been formed thereon. Because the wafer has the circuitry formed thereon, it is difficult to form the through silicon vias due to the obstruction of the circuit. Furthermore, even if the through silicon vias can be formed, the existing circuitry may still be damaged during the electroplating or vacuum deposition process applied for filling the through silicon vias. Because the formation of the circuitry on the wafer is completed, the insulation problem for the through silicon vias may exist. Furthermore, the surface...

AI Technical Summary

Benefits of technology

[0005]The objective of the present invention is to provide a method for packaging a wafer in which the through silicon vias and the redistribution layer are formed on a bare wafer before the semiconductor circuits are formed on the bare wafer so that the circuits subsequently formed on the wafer will not be damaged. In addition, the breakage or the crack on the wafer will not occur during the movement of the wafer. The upper metal layer and the underlying silicon wafer have a plurality of connection members which allow a plurality of chips to be easily stacked together without wire bonding. Therefore, chip scale packaging can be easily achieved.

[0008]In the present invention, the cost for the substrate, the wire bonding, and molding / encapsulating process can be reduced. Because the second chip is very thin, the connection members are provided on both the upper and lower surfaces of the chip so that the chips can be stacked on top of each other and electrically coupled to each other without involving the complicated wire bonding and alignment processes. Therefore, in the present invention, a high density chip packaging becomes possible without any limitation, and thereby the conventional packaging space limitation can be overcome. Accordingly, Multi-chip packaging (MCP) or system in packaging (SiP) thus can be performed at the wafer level.

Problems solved by technology

Because the wafer has the circuitry formed thereon, it is difficult to form the through silicon vias due to the obstruction of the circuit.

Furthermore, even if the through silicon vias can be formed, the existing circuitry may still be damaged during the electroplating or vacuum deposition process applied for filling the through silicon vias.

Because the formation of the circuitry on the wafer is completed, the insulation problem for the through silicon vias may exist.

Furthermore, the surface of the wafer may be damaged during forming a redistribution layer.

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