Semiconductor interconnect structure having enhanced performance and reliability

Active Publication Date: 2013-03-28
GLOBALFOUNDRIES US INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0011]The present invention relates to a structure and method for fabricating an interconnect structure having enhanced performance

Problems solved by technology

However, when copper is utilized to form interconnects, electromigration may occur.
Electromigration can result in void formation as well as extrusion/hillock formation along regions of an interconnect structure.
The voids can result in an open circuit if one or more voids formed are large enough to sever the interconnect structure, and the extrusions/hillocks can result in a short circuit if one or more extrusions/hillocks are sufficiently long to form a region of abnormally low electrical impedance.
The oxidized barrier interface is susceptible to serving as an electromigration void nucleation site, which can result in faster growth of large electromigration voids.
Specifically, oxygen that intrudes the seed layer and electroplated copper layer may consume impurities within the interconnect structure, for example manganese and aluminum impurities, and prevent the impurities from segregating in certain regions of the interconnect structure that are susceptible to copper diffusion.
Copper diffusio

Method used

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  • Semiconductor interconnect structure having enhanced performance and reliability
  • Semiconductor interconnect structure having enhanced performance and reliability
  • Semiconductor interconnect structure having enhanced performance and reliability

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Embodiment Construction

[0018]Exemplary embodiments now will be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0019]The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms “a”, “an”, etc., do not denot...

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Abstract

An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by minimizing oxygen intrusion into a seed layer and an electroplated copper layer of the interconnect structure, are disclosed. At least one opening in a dielectric layer is formed. A sacrificial oxidation layer disposed on the dielectric layer is formed. The sacrificial oxidation layer minimizes oxygen intrusion into the seed layer and the electroplated copper layer of the interconnect structure. A barrier metal layer disposed on the sacrificial oxidation layer is formed. A seed layer disposed on the barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the sacrificial oxidation layer, the barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a semiconductor integrated circuit interconnect structure and method for fabricating an interconnect structure having enhanced performance and reliability, by minimizing oxygen intrusion into a seed layer and an electroplated copper layer of the interconnect structure.[0003]2. Description of the Related Art[0004]Semiconductor devices include a plurality of circuit components (i.e., transistors, resistors, diodes, capacitors, etc.) connected together to form an integrated circuit fabricated on a semiconductor substrate. A complex network of semiconductor integrated circuit interconnects (interconnects) are routed to connect the circuit components distributed on the surface of the substrate. Efficient routing of these interconnects, across semiconductor devices, requires formation of multi-level or multi-layered patterning schemes, such as single or dual damascene interconnect structures.[...

Claims

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Application Information

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IPC IPC(8): H01L23/482H01L21/768
CPCH01L23/53238H01L21/76831H01L21/76846H01L21/76849H01L23/53266H01L21/76873H01L23/5226H01L23/53209H01L23/53223H01L21/76867H01L2924/0002H01L2924/00
Inventor CABRAL, JR., CYRILDUBOIS, GERAUD JEAN-MICHELEDELSTEIN, DANIEL C.NOGAMI, TAKESHISANDERS, DANIEL P.
Owner GLOBALFOUNDRIES US INC
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