Charge compensation calibration for high resolution data converter

Abstract

A calibrating Analog-to-Digital Converter (ADC) has an X-side array with binary-weighted capacitors that connect to an X-side line and a Y-side array connected to a Y-side line. Each array has binary-weighted capacitors from a most-significant-bit (MSB) to a least-significant-bit (LSB), but the LSB capacitor is duplicated as a termination capacitor and a middle capacitor between upper and lower groups is also duplicated as a surrogate capacitor. During calibration, lower array capacitors are switched low while the upper capacitors are driven by a thermometer-code value on both X and Y arrays. The thermometer value is inverted to the X-array but remains uninverted on the Y array. The lower array bits are tested to final a calibration value that has X and Y side voltages balanced.

Description

FIELD OF THE INVENTION[0001]This invention relates to analog-to-digital converters (ADC), and more particularly to calibration methods to improve the precision of successive-approximation register (SAR) ADC's.BACKGROUND OF THE INVENTION[0002]Both analog and digital circuits are often present in system chips. Signals may cross from the digital domain to the analog domain, and vice-versa. Analog signals may be converted to digital for complex digital processing, such as by a Digital Signal Processor (DSP).[0003]Many types of Analog-to-Digital Converters (ADC's) have been used for a wide variety of applications. Flash ADC's compare analog signal voltages to multiple voltage levels in an instant to produce a multi-bit digital word that represents the analog voltage. Successive-approximation ADC's use a series of stages to convert an analog voltage to digital bits. Each stage compares an analog voltage to a reference voltage, producing one digital bit. In sub-ranging ADC's, each stage co...

AI Technical Summary

Benefits of technology

The patent text describes a method for improving the precision of analog-to-digital converters (ADCs) called successive-approximation register (SAR) ADCs. The invention relates to calibration methods for SAR ADCs to improve their accuracy. The technical effect of the invention is to provide a more accurate and reliable conversion of analog signals to digital signals.

Problems solved by technology

While such capacitor-array DAC's are useful, the large size of the MSB capacitors requires a large amount of charge to be transferred.

Inherent device and impedance mismatches in deep sub-micron processes limit converter resolutions to about 10 bits.

Another source of errors is charge injection and clock feed-through caused by switches that connect and disconnect capacitors.

Clock feed-through can be different for the main array and for the calibration array of capacitors, thus introducing voltage imbalances and measurement errors.

When the switching sequences differ, errors measurement may occur.

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