Reduced residual offset sigma delta analog-to-digital converter (ADC) with chopper timing at end of integrating phase before trailing edge

a residual offset and analog-to-digital converter technology, applied in analogue/digital conversion, instruments, transmission systems, etc., can solve problems such as errors in chopper stabilization and more charge under their channels

Active Publication Date: 2013-06-06
HONG KONG APPLIED SCI & TECH RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, these larger transistors also have a larger capacitance and thus have more charge under their channels when turned on.
Injected charges 150 may be injected just before chopper clocks C1, C2 switch, causing errors in chopper stabilization.

Method used

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  • Reduced residual offset sigma delta analog-to-digital converter (ADC) with chopper timing at end of integrating phase before trailing edge
  • Reduced residual offset sigma delta analog-to-digital converter (ADC) with chopper timing at end of integrating phase before trailing edge
  • Reduced residual offset sigma delta analog-to-digital converter (ADC) with chopper timing at end of integrating phase before trailing edge

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Embodiment Construction

[0026]The present invention relates to an improvement in chopper-stabilized sigma-delta modulators. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

[0027]The inventors have realized that the prior-art chopper-clock timing is undesirable since charge is injected by the phase clock turning off just before the chopper clocks change. The injected charge occurs at a critical time when node voltages should be stable. The inventors further realize that chopper ...

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Abstract

An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.

Description

FIELD OF THE INVENTION[0001]This invention relates to sigma-delta modulators, and more particularly for clock-timing improvements for chopper stabilization of amplifiers.BACKGROUND OF THE INVENTION[0002]Sigma-delta modulators are widely used in consumer audio and precision measurement devices, such as 24-bit audio analog-to-digital converters (ADC). Signal processing is performed in the digital domain rather than in the analog domain, allowing for power savings and performance improvements as semiconductor processes improve. The sigma-delta modulator samples the input signal at a much higher frequency and spreads noise over a wider frequency band. Such over-sampling and noise shaping can provide higher levels of linearity and dynamic range.[0003]Chopper stabilization is sometimes used to shift the noise to a higher frequency, and then to remove the noise after amplification. One multiplier is inserted before the input of the first-stage amplifier, while a second multiplier is insert...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H03M3/02H03M1/12
CPCH03M3/34H03M3/454H03M3/43
Inventor CHAN, KWAI CHI
Owner HONG KONG APPLIED SCI & TECH RES INST
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