Timing analysis of an array circuit cross section

Inactive Publication Date: 2013-07-18
GLOBALFOUNDRIES INC
View PDF3 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent text describes a method for analyzing timing in an array circuit. It involves receiving a set of pins to be timed and selecting a specific section of the circuit that includes those pins. From there, a backtrace is performed to identify bus groups with multiple timing pins. The timing of an assigned pin in a first bus group is calculated based on the timing of a surrogate pin in that group. The technical effect of this method is to provide a reliable and efficient way to analyze timing in complex array circuits.

Problems solved by technology

Testing a full extracted netlist of the whole circuit design such as static timing analysis could be prohibitively expensive and time consuming.
However, creating a cross section netlist is often time consuming and may not match the characteristics of the underlying circuit design.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Timing analysis of an array circuit cross section
  • Timing analysis of an array circuit cross section
  • Timing analysis of an array circuit cross section

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0041]FIG. 5 is a high level flowchart of performing timing analysis of a cross section of the array circuit in accordance with a This embodiment is implemented with a designer or tester providing a list of cells to be tested such as by static timing analysis and a list of external pins which may be driven during such timing analysis by the cells listed.

[0042]In a first step 500, the circuit design and various constraints of the array circuit is read or otherwise accessed by the timing analysis software. This provides the information needed for the timing analysis software to initiate constructing a cross section timing model of the array circuitry prior to performing static timing analysis of that timing model. This step is described in greater detail below with respect to FIG. 6A. In a second step 510, a backtrace of pins or nets in the netlist is performed. This allows the timing analysis software to determine which portions of the netlist may be relevant for constructing a timi...

second embodiment

[0061]FIG. 8 is a high level flowchart of performing timing analysis of the cross section of the array circuit in accordance with the This embodiment is implemented with a designer or tester providing a list of cells to be tested such as by static timing analysis. Due to the capability of forward tracing, this embodiment does not require the designer or tester to provide a list of external pins which may be driven during such timing analysis.

[0062]In a first step 800, the circuit design and various constraints of the array circuit is read or otherwise accessed by the timing analysis software. This provides the information needed for the timing analysis software to initiate constructing a test model of the array circuitry. This step is described in greater detail above with respect to FIG. 6A. In a second step 810, a backtrace of nets in the netlist is performed. This allows the timing analysis software to determine which portions of the netlist are relevant for constructing a timin...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A method, system or computer usable program product for performing timing analysis on an array circuit including receiving in memory a set of pins to be timed, selecting with a data processor a cross section of the array circuit including the set of pins wherein a backtrace is performed from the set of pins to identify a set of bus groups, each bus group having a plurality of timing pins, and assigning timing for an assigned pin of a first bus group equal to timing calculated for a surrogate pin of the first bus group based on array circuit regularity.

Description

BACKGROUND[0001]1. Technical Field[0002]The present invention relates generally to timing analysis of an array, and in particular, to a computer implemented method for timing analysis of a cross section of an array circuit design.[0003]2. Description of Related Art[0004]Semiconductor memory designers test their circuit designs to check for a variety of issues including functionality, robustness and timing prior to having those designs implemented in silicon. For memory arrays, these circuit designs may be a schematic design in combination with a layout design. For testing, a netlist is extracted from the circuit design. A netlist generally conveys connectivity information and may include instances, nets and their attributes. An instance is a description of a part or device such as a transistor, resistor, capacitor or integrated circuit and may include a description of the device, the connections that can be made (“pins”) to the device, and the basic properties of the device. Nets ar...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F17/50
CPCG06F2217/84G06F17/5031G06F30/3312G06F2119/12
InventorTHOZIYOOR, SHYAMKUMARKIM, TAE H.LEE, SANG Y.
OwnerGLOBALFOUNDRIES INC