Semiconductor device having hierarchical structured bit lines

a technology of semiconductor devices and bit lines, applied in the field of semiconductor devices with hierarchical structure, can solve the problems of increasing reducing the apparent information-holding capacity of memory cells previously restored, and small timing margin of control, so as to achieve the effect of reducing the parasitic capacitance of global bit lines

Inactive Publication Date: 2014-01-02
LONGITUDE SEMICON S A R L
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This configuration ensures sufficient operation margins for sense amplifiers and avoids issues associated with time division restore operations, maintaining high sensitivity and efficient data transfer.

Problems solved by technology

However, according to the semiconductor device described in Japanese Patent Application Laid-open No. 2000-114491, because switches are provided in the middle of global bit lines, a parasitic capacitance of the global bit lines increase due to an ON resistance of the switches.
Further, because positions of the switches which are turned ON change depending on positions of memory cells to be accessed, a parasitic capacitance connected to one sense amplifier and a parasitic capacitance connected to the other sense amplifier do not necessarily match at a time of a sense operation, and also change at each access.
Therefore, a timing margin of control is small.
Furthermore, because restore timings of the two memory cells are different, an apparent information-holding capacity of the memory cell previously restored decreases.
Furthermore, because the restore operation using the first sense amplifier and the restore operation using the second sense amplifier can be performed simultaneously, various problems that can occur at the time of performing a restore operation by time division do not occur.

Method used

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  • Semiconductor device having hierarchical structured bit lines
  • Semiconductor device having hierarchical structured bit lines
  • Semiconductor device having hierarchical structured bit lines

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0024]FIG. 1 is a circuit diagram showing a main part of a semiconductor device 10 according to the present invention.

[0025]As shown in FIG. 1, the semiconductor device 10 according to the first embodiment is a semiconductor memory having hierarchized bit lines, and is configured to have two sense amplifiers connected to a pair of global bit lines as high-order bit lines. More specifically, the semiconductor device 10 according to the first embodiment includes a pair of global bit lines GBLTi and GBLBi (i=0, 1, 2, . . . ) extended in a Y direction, a sense amplifier SAi provided at one end of the pair of global bit lines GBLTi and GBLBi, and a sense amplifier SAiA provided at the other end of the pair of global bit lines GBLTi and GBLBi. Circuit formats of the sense amplifiers SAi and SAiA are not particularly limited, and a flip-flop circuit can be used, for example. The pair of global bit lines GBLTi and GBLBi have a so-called folded structure.

[0026]A sense switch SSW0i (first sen...

second embodiment

[0056]the present invention is explained next.

[0057]FIG. 5 is a circuit configuration showing a main part of a semiconductor device 20 according to the second embodiment.

[0058]As shown in FIG. 5, the semiconductor device 20 according to the second embodiment is different from the semiconductor device 10 according to the first embodiment in that a local I / O line LIO0 is allocated to the sense amplifier SAi, and a local I / O line LIO1 is allocated to the sense amplifier SAiA. Because other features of the semiconductor device 20 are identical to those of the semiconductor device 10, like elements are denoted by like reference numerals and redundant explanations thereof will be omitted.

[0059]The local I / O line LIO0 is a complementary wiring including local I / O lines LIOT0 and LIOB0. When a column switch YSW0i is in a conductive state, data of the global bit line GBLTi amplified by the sense amplifier SAi is supplied to the local I / O line LIOT0, and data of the global bit line GBLBi ampl...

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Abstract

A semiconductor device includes first and second global bit lines; first, second, third and fourth sense node; a first sense switch coupled between the first sense node and the first global bit line; a second sense switch coupled between the second sense node and the second global bit line; a third sense switch coupled between the third sense node and the first global bit line; a fourth sense switch coupled between the fourth sense node and the second global bit line; a first sense amplifier including a first terminal coupled to the first sense node and a second terminal coupled to the second sense node; a second sense amplifier including a third terminal coupled to the third sense node and a fourth terminal coupled to the fourth sense node. The first, second, third and fourth terminals respectively have first, second, third and fourth parasitic capacitances substantially equal in capacitance value.

Description

[0001]This Application is a Continuation Application of U.S. patent application Ser. No. 12 / 926,693, having a U.S. filing date of Dec. 3, 2010, now U.S. Pat. No. ______.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device in which bit lines have a hierarchical structure.[0004]2. Description of Related Art[0005]Among semiconductor devices represented by DRAM (Dynamic Random Access Memory), there are devices in which bit lines thereof are hierarchized into local bit lines and global bit lines (see Japanese Patent Application Laid-open Nos. 2000-114491, H11-163292, and H8-87880). The local bit lines are low-order bit lines and are connected to memory cells. Meanwhile, the global bit lines are high-order bit lines and are connected to sense amplifiers. When bit lines are hierarchized, the number of memory cells allocated to one sense amplifier can be increased whil...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): G11C5/06
CPCG11C5/06G11C7/08G11C11/4091G11C11/4097H10B12/053H10B12/482G11C2207/002G11C2207/005
InventorSATO, TAKENORIKAJIGAYA, KAZUHIKOYANAGAWA, YOSHIMITSUSEKIGUCHI, TOMONORIKOTABE, AKIRAAKIYAMA, SATORU
OwnerLONGITUDE SEMICON S A R L