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Method for patterning semiconductor structure

a semiconductor structure and patterning technology, applied in semiconductor/solid-state device manufacturing, basic electric elements, electric instruments, etc., can solve the problems of limited critical dimension (cd) of the pattern for the mask, and the distortion of the electrical characteristic of the devi

Active Publication Date: 2014-09-11
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach effectively reduces pattern distortion and maintains desired pattern integrity, allowing for precise transfer of patterns to semiconductor structures without significant electrical characteristic degradation.

Problems solved by technology

The critical dimension (CD) of the pattern for the mask is limited to the resolution limit of the optical exposure tool.
The electrical characteristic of the device is affected by the distortion.

Method used

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  • Method for patterning semiconductor structure
  • Method for patterning semiconductor structure
  • Method for patterning semiconductor structure

Examples

Experimental program
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Embodiment Construction

[0011]FIGS. 1-8 illustrate a method for patterning a semiconductor structure according to one embodiment.

[0012]Referring to FIG. 1, a first film structure 102 may comprise a substrate 104, a dielectric layer 106, a hard mask layer 108, a dielectric layer 110, a hard mask layer 112, an etching stop layer 114, a dielectric layer 116, an anti-reflection layer 118 and a photoresist layer 120. For example, the substrate 104 may comprise a silicon substrate or other suitable semiconductor substrates. The dielectric layer 106 may comprise a pad oxide. The hard mask layer 108 may comprise a nitride such as silicon nitride. The dielectric layer 110 may comprise an oxide such as silicon oxide. The hard mask layer 112 may comprise an advanced patterning film (APF) (Applied

[0013]Materials Inc.). The etching stop layer 114 may comprise an oxide such as SiOC. The dielectric layer 116 may comprise an oxide such as silicon oxide. The anti-reflection layer 118 may comprise a bottom anti-reflective c...

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PUM

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Abstract

A method for patterning a semiconductor structure is provided. The method comprises following steps. A first mask defining a first pattern in a first region and a second pattern in a second region adjacent to the first region is provided. The first pattern defined by the first mask is transferred to a first film structure in the first region, and the second pattern defined by the first mask is transferred to the first film structure in the second region. A second film structure is formed on the first film structure. A second mask defining a third pattern in the first region is provided. At least 50% of a part of the first region occupied by the first pattern defined by the first mask is identical with a part of the first region occupied by the third pattern defined by the second mask.

Description

BACKGROUND[0001]1. Technical Field[0002]The disclosure relates to a method for patterning a semiconductor structure, and more particularly to a method using two masks having similar patterns for patterning a semiconductor structure.[0003]2. Description of the Related Art[0004]For forming a designed integrated circuit to a semiconductor wafer, a mask formed with a design layout pattern is provided. The layout pattern defined by the mask is transferred on to a photoresist layer on a surface of a semiconductor structure and then transferred into the semiconductor structure by photolithography processes. Therefore, the photolithography process is an important key for the semiconductor manufacturing.[0005]The critical dimension (CD) of the pattern for the mask is limited to the resolution limit of the optical exposure tool. With the trend towards high integration and small pattern of the circuit design, the deviation or the distortion of the pattern transferred into the semiconductor str...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/308
CPCH01L21/308H10B10/18
Inventor HUANG, CHIA-WEICHEN, MING-JUITSENG, TING-CHENGHSIEH, PING-I
Owner UNITED MICROELECTRONICS CORP