Methods of forming stressed multilayer finfet devices with alternative channel materials

Abstract

Disclosed are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods involve forming such alternating layers of different semiconductor materials in a cavity formed above the substrate fin and thereafter forming a gate structure around the fin using gate first or gate last techniques.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of forming stressed multilayer FinFET devices with alternative channel materials.[0003]2. Description of the Related Art[0004]The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel re...

AI Technical Summary

Benefits of technology

Enhances the performance of FinFET devices by effectively inducing stress in the channel region, improving operational speed and reducing short channel effects, while allowing for the use of alternative materials that can enhance low-voltage operation.

Problems solved by technology

However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region.

In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain.

However, when it comes to FinFET devices, the formation of such stressed nitride layers on the source / drain regions is not as effective at inducing the desired stress characteristics in the channel region of the FinFET device.

This is believed to be due to the remoteness of the source / drain regions and the structural differences between planar and FinFET devices.

Thus, device designers spend a great amount of time and effort to maximize device performance while seeking ways to reduce manufacturing costs and improve manufacturing reliability.

However, the integration of such alternative materials on silicon substrates (the dominant substrates used in the industry) is a non-trivial matter due to, among other issues, the large difference in lattice constants between such materials and silicon.

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