Nano-scale structures

Abstract

A nanoscale structure includes an array of pillars over an underlying layer, a separation wall layer including first separation walls formed over sidewalls of the pillars, and a block co-polymer (BCP) layer formed over the separation wall layer and filling gaps between the pillars. The BCP layer is phase-separated to include first domains that provide second separation walls formed over the first separation walls and second domains that are separated from each other by the first domains.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS[0001]This application is a continuation-in-part of U.S. patent application Ser. No. 14 / 139,502, filed on Dec. 23, 2013, which claims the priority of Korean Patent Application No. 10-2013-0088353, filed on Jul. 25, 2013 in the Korean Intellectual Property Office.BACKGROUND[0002]1. Technical Field[0003]Embodiments of the present disclosure relate to nano-scale structures, and more particularly, to nano-scale structures used in fabrication of a semiconductor device having an array of fine patterns.[0004]2. Related Art[0005]In fabrication of electronic devices such as semiconductor devices, many efforts have been focused to integrate more patterns in a limited area of a semiconductor substrate. That is, attempts to increase the integration density of the electronic devices or the semiconductor devices have typically resulted in formation of fine patterns. Various techniques have been proposed to form the fine patterns such as small contact holes ...

AI Technical Summary

Benefits of technology

The patent text describes various embodiments of nanoscale structures for semiconductor devices. These structures include pillars, separation walls, and a block co-polymer layer. The block co-polymer layer is formed over the separation walls and fills gaps between the pillars. The block co-polymer layer is phase-separated into first and second domains, which provide the second separation walls and separate the structure into different sections. The nanoscale structures can be used for various semiconductor applications, such as memory devices or logic devices.

Problems solved by technology

In the event that the fine patterns of the semiconductor devices are formed using only a photolithography process, there may be some limitations in forming the fine patterns due to image resolution limits of lithography apparatuses used in the photolithography process.

However, the methods of forming the fine patterns using the self-assembly technique are still under development.

Thus, there may be still some difficulties in forming the fine patterns of highly integrated semiconductor devices using the self-assembly technique.

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