Methods for forming finfets having a capping layer for reducing punch through leakage

Abstract

A method for forming FinFETs having a capping layer for reducing punch through leakage includes providing an intermediate semiconductor structure having a semiconductor substrate and a fin disposed on the semiconductor substrate. A capping layer is disposed over the fin, and an isolation fill is disposed over the capping layer. A portion of the isolation fill and the capping layer is removed to expose an upper surface portion of the fin. Tapping layer and a lower portion of the fin define an interface dipole layer barrier, a portion of the capping layer operable to provide an increased negative charge or an increased positive charge adjacent to the fin, to reduce punch-through leakage compared to a fin without the capping layer.

Description

TECHNICAL FIELD[0001]The present disclosure relates generally to conductive circuits and methods of forming conductive circuits, and more particularly, a capping treatment of a fin in the fabrication of a FinFET structure to reduce punch-through leakage.BACKGROUND OF THE DISCLOSURE[0002]Fin field-effect transistors (FinFET) devices have been developed to replace conventional planar bulk MOSFETs in advanced CMOS technology due to their improved short-channel effect immunity and Ion / Ioff ratio. However, a problem with bulk short channel FinFET devices, is that a leakage path from source to drain exists through a portion of the fin not covered by the gate, but lies below the channel. The leakage of current from source to drain through the lower (un-gated) part of the fin that is not covered by the gate, commonly known as punch-through leakage, causes an increase of static power consumption which is undesirable in modern submicron devices.[0003]In one solution, punch-through leakage in ...

AI Technical Summary

Benefits of technology

The patent text describes a method and structure for reducing punch-through leakage in a semiconductor device. The method involves removing portions of a capping layer and an isolation fill to expose some fins, and then adding a new capping layer and isolation fill to form an interface dipole layer barrier. The new capping layer can provide a negative or positive charge to reduce leakage compared to fins without the capping layer. The structure includes the capping layer and isolation fill over the fin, which also acts as an interface dipole layer barrier. Overall, this method and structure improve the reliability and performance of semiconductor devices.

Problems solved by technology

However, a problem with bulk short channel FinFET devices, is that a leakage path from source to drain exists through a portion of the fin not covered by the gate, but lies below the channel.

The leakage of current from source to drain through the lower (un-gated) part of the fin that is not covered by the gate, commonly known as punch-through leakage, causes an increase of static power consumption which is undesirable in modern submicron devices.

However, the impurities doped by the punch-through-stopper (PTS) implantation may diffuse into the channel region, increasing the variability due to random dopant fluctuation (RDF) and lowering the carrier mobility of the channel region.

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