Methods for forming finfets having a capping layer for reducing punch through leakage

Abstract

A method for forming FinFETs having a capping layer for reducing punch through leakage includes providing an intermediate semiconductor structure having a semiconductor substrate and a fin disposed on the semiconductor substrate. A capping layer is disposed over the fin, and an isolation fill is disposed over the capping layer. A portion of the isolation fill and the capping layer is removed to expose an upper surface portion of the fin. Tapping layer and a lower portion of the fin define an interface dipole layer barrier, a portion of the capping layer operable to provide an increased negative charge or an increased positive charge adjacent to the fin, to reduce punch-through leakage compared to a fin without the capping layer.

Description

TECHNICAL FIELD[0001]The present disclosure relates generally to conductive circuits and methods of forming conductive circuits, and more particularly, a capping treatment of a fin in the fabrication of a FinFET structure to reduce punch-through leakage.BACKGROUND OF THE DISCLOSURE[0002]Fin field-effect transistors (FinFET) devices have been developed to replace conventional planar bulk MOSFETs in advanced CMOS technology due to their improved short-channel effect immunity and Ion / Ioff ratio. However, a problem with bulk short channel FinFET devices, is that a leakage path from source to drain exists through a portion of the fin not covered by the gate, but lies below the channel. The leakage of current from source to drain through the lower (un-gated) part of the fin that is not covered by the gate, commonly known as punch-through leakage, causes an increase of static power consumption which is undesirable in modern submicron devices.[0003]In one solution, punch-through leakage in ...

AI Technical Summary

Benefits of technology

[0006]In another aspect, a method includes providing a semiconductor substrate and a plurality of fins disposed on the semiconductor substrate, providing a first capping layer disposed over the fins, and a first isolation fill disposed over the first capping layer. A portion of the capping layer and the first isolation fill is removed to expose some of the fins. A second capping layer is disposed over the exposed fins, and a second isolation fill over the second capping layer. The second capping layer is different from the first capping layer. A portion of the first and second capping layers and the first and second isolation fills are removed to expose upper surface portions of the fins. The capping layers and the lower portions of the fins define interface dipole layer barriers. Portions of the capping layers are operable to provide increased negative charges or increased positive charges adjacent to the fins, to reduce punch-through leakage compared to fins not having the capping layers.

[0007]In another aspect, a semiconductor structure includes a semiconductor substrate, and a fin disposed on said substrate having an upper portion and a lower portion. A capping layer is disposed over a lower surface portion of the fin and an isolation fill is disposed over the capping layer. The capping layer and a lower portion of the fin define an interface dipole layer barrier to reduce punch-through leakage compared to a fin without the capping layer. A portion of the capping layer operable to provide an increased negative charge or an increased positive charge adjacent to the fin,

Problems solved by technology

However, a problem with bulk short channel FinFET devices, is that a leakage path from source to drain exists through a portion of the fin not covered by the gate, but lies below the channel.

The leakage of current from source to drain through the lower (un-gated) part of the fin that is not covered by the gate, commonly known as punch-through leakage, causes an increase of static power consumption which is undesirable in modern submicron devices.

However, the impurities doped by the punch-through-stopper (PTS) implantation may diffuse into the channel region, increasing the variability due to random dopant fluctuation (RDF) and lowering the carrier mobility of the channel region.

Images