Integrated circuit structure having thin gate dielectric device and thick gate dielectric device

Abstract

One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.

Description

BACKGROUNDTechnical Field[0001]The present disclosure relates to integrated circuits, and more particularly, to integrated circuit structures having a thin gate dielectric device and a thick gate dielectric device, and a method of forming the same.Related Art[0002]In integrated circuit (IC) structures, a transistor is a critical component for implementing digital circuitry designs. Generally, a transistor includes three electrical terminals: a source, a drain, and a gate. By applying different voltages to the gate terminal, the flow of electric current from the source to the drain can be turned on and off. A common type of transistor is a metal oxide field effect transistor (MOSFET). One type of MOSFET structure is a “FINFET,” typically formed upon a semiconductor-on-insulator (SOI) layer and buried insulator layer. A FINFET can include a semiconductor structure etched into a “fin” shaped body, with one side of the fin acting as a source terminal and the other side of the fin acting...

AI Technical Summary

Benefits of technology

This patent text is related to a method and structure for making an integrated circuit with thin and thick gate dielectric devices. The method involves depositing a nitrided oxide layer over each fin in the set of fins within a substrate, adding a conformal carbon hard mask, patterning a photoresist stack, and removing the exposed carbon hard mask and other layers to create the structure. An interfacial layer is also included in the thin gate dielectric device region for better performance. The structure includes a thin gate dielectric device and a thick gate dielectric device with an interfacial layer and nitrided oxide layer. The technical effects include improved performance and reliability of the integrated circuit.

Problems solved by technology

However, the smaller dimensions associated with multi-gate FETs (as compared to single-gate FETs) necessitate greater control over performance issues such as short channel effects, punch-through, metal-oxide semiconductor (MOS) leakage current, and the parasitic resistance that is present in a multi-gate FET.

That is, the deposition of the sacrificial oxide and subsequent removal of the same compromises the quality of the gate dielectric that needs to be retained and can lead to device and parametric shift from ideal characteristics desired.

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