Mixer bias circuit

Abstract

The present invention discloses a mixer bias circuit including a first reference voltage generation circuit, an amplifier, a first transistor array, a first switch array, a second reference voltage generation circuit, a second transistor array, a second switch array, a first resistive component, and a second resistive component. The mixer bias circuit provides multiple bias voltages by dynamically tracking the common mode voltage of a trans-impedance amplifier (TIA) and compensates for imbalance and mismatch effects by asymmetrically trimming the bias voltages to improve the second-order intercept point of a radio frequency (RF) receiver front-end (RXFE).

Description

BACKGROUND OF THE INVENTION1. Field of the Invention[0001]The present invention generally relates to a mixer bias circuit, and, more particularly, to a mixer bias circuit having a second-order intercept point (hereinafter referred to as IP2) calibration function.2. Description of Related Art[0002]Despite its wide use in a radio frequency (RF) transceiver due to its high integration and low power consumption, a mixer comprising metal-oxide-semiconductor field-effect transistors (MOSFETs) confronts some design challenges such as low output direct current (DC) offset and high linearity characterized by the IP2 and the third-order intercept point (hereinafter referred to as IP3). A conventional receiver can be implemented with a direct-conversion architecture, as shown in FIG. 1. The antenna 101 receives a downlink (DL) RF signal, and outputs the received DL RF signal to a low-noise amplifier (LNA) 110 via an antenna interface unit 105. The antenna interface unit 105 may be consisted of...

AI Technical Summary

Benefits of technology

[0012]The mixer bias circuit of the present invention provides a plurality of bias voltages by dynamically tracking the common-mode voltage of the TIA and compensates for imbalance and mismatch effects by asymmetrically trimming the bias voltages to thereby improve the IP2 at the radio frequency (RF) receiver front-end (RXFE).

Problems solved by technology

Generally, the performance of a mixer suffers from various effects such as imbalance, mismatch, temperature, and fabrication process, subsequently influencing the IP2, DC offset, and image rejection ratio (IMR) performances of an RF RXFE.

However, those proposed techniques are possibly under the influence of a common-mode voltage variation induced by a TIA, resulting in an IP2 degradation of the calibrated mixer.

However, the nonlinear components such as the third order intermodulation distortion (hereinafter referred to as IMD3) and IMD2 would degrade the sensitivity of the RF RXFE.

Additionally, the mismatch and asymmetrical effects existing in the electronic devices of a mixer would enlarge the IMD2.

However, the proposed IP2 calibration techniques still suffer from the common-mode voltage variation from a TIA, leading to a degradation of the optimized IP2.

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