Reconfigurable circuit and the method for using the same

Inactive Publication Date: 2020-09-17
NEC CORP
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent text is explaining a technology that helps improve the efficiency of solar cells. The technology involves using a special coating on the surface of the solar cell that helps to capture and convert sunlight into electrical energy. This results in a more effective and efficient solar cell that can produce more energy from the same amount of sunlight.

Problems solved by technology

The relatively large energy consumption of FPGAs limits integration of commercial FPGAs into IoT (Internet of Things) devices.
This causes extremely large area overhead, cost, and energy consumption in FPGAs.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Reconfigurable circuit and the method for using the same
  • Reconfigurable circuit and the method for using the same
  • Reconfigurable circuit and the method for using the same

Examples

Experimental program
Comparison scheme
Effect test

first exemplary embodiment

[0033]FIG. 2 illustrates a reconfigurable circuit according to a first exemplary embodiment of the present invention. The reconfigurable circuit includes: first line L1; first switch element SW1 disposed between first line L1 and a first power source line of voltage V1; second line L2; second switch element SW2 disposed between second line L2 and a second power source line of voltage V2; and resistive switch assembly 111 disposed between first line L and second line L2. The voltages V1 and V2 are different from each other. Resistive switch assembly 111 includes: first NVRS (non-volatile resistive switch) S1; and second NVRS S2 whose first end is coupled to the first end of the first NVRS S1. The second end of first NVRS S1 is coupled to first line L1, and the second end of second NVRS S2 is coupled to second line L2. For the purpose of explanation, terminals T1 and T2 are illustrated at ends of first line L1 and second line L2, respectively, in FIG. 2. Terminal T3 is connected to th...

second exemplary embodiment

[0047]Next, applications of the above-mentioned reconfigurable circuit will be described. FIG. 8 illustrates the reconfigurable circuit according to the second exemplary embodiment in which a plurality of first lines and a plurality of second lines are arranged and the resistive switch assembly including two NVRSs serially connected to each other is disposed at each cross-point between the first lines and the second lines. In the drawing, the first lines extend in the vertical direction while the second lines extend in the horizontal direction. In the present embodiment too, each resistive switch assembly is a one-input-two-output NB (Nonobridge®) which is used both for a data routing switch between the first line and the second line, and for a memory cell.

[0048]In the example shown in FIG. 8, two first or vertical lines LV0, LV1 and two second or horizontal lines LH0, LH1 are arranged in a lattice manner and a resistive switch assembly or Nonobridge® is arranged at each cross-point...

third exemplary embodiment

[0060]The reconfigurable circuit based on the present invention can be also applied to time-multiplexed crossbar or interconnect structures, such as proposed in [PTL 3], in which a plurality of switches are arranged at each of cross-points between horizontal lines and vertical lines and the switches are selected in time-divisional manner such that two or more switches are not simultaneously selected. The time-multiplexed crossbar achieves time-divisional changeover of contexts in FPGA. The selection of the switches is performed by using a pass transistor interposed in each switch. Time control signals are applied to the respective pass transistors at each cross-point. Since the selection using the pass transistor can be rapidly executed, the time-multiplex crossbar configuration provides runtime-changeable data signal routing which improves flexibility of FPGA.

[0061]FIG. 13 illustrates an example of a reconfigurable circuit according to a third exemplary embodiment in which a plural...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A reconfigurable circuit comprising: a first line; a first switch element disposed between the first line and a first power source line of first voltage; a second line; a second switch element disposed between the second line and a second power source line of second voltage which is different from the first voltage; and a resistive switch assembly disposed between the first line and the second line. The resistive switch assembly including a first non-volatile resistive switch, and a second non-volatile resistive switch whose first end is coupled to a first end of the first non-volatile resistive switch. The second end of the first non-volatile resistive switch is coupled to the first line, and the second end of the second non-volatile resistive switch is coupled to the second line.

Description

TECHNICAL FIELD[0001]The present invention relates to a reconfigurable circuit with non-volatile resistive switches, and the method for using the reconfigurable circuit.BACKGROUND ART[0002]A typical semiconductor integrated circuit (IC) is constructed by transistors build on a semiconductor substrate and upper layer wires used to connect the transistors. The patterns of the transistors and wires are determined in a design stage of the IC. Interconnections between the transistors and wires cannot be changed after fabrication. In order to improve flexibility of IC, field-programmable gate arrays (FPGAs) have been proposed and developed. In FPGAs, configuration data including operation and interconnection information is stored in memories, so that different logic operations and interconnections can be realized by configuring the memories after fabrication according to requirements of end users. Interconnections within FPGA can be altered by controlling ON-and-OFF of switches in a routi...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H03K19/177
CPCH03K19/177H03K19/17736H03K19/1737H03K19/17704H03K19/17744H03K19/17784H03K19/17796
InventorBAI, XUSAKAMOTO, TOSHITSUGUTSUJI, YUKIHIDEMIYAMURA, MAKOTOTADA, AYUKANEBASHI, RYUSUKE
OwnerNEC CORP