Gate devices and methods of formation using angled ions

Abstract

The present disclosure is directed to structures and processing for three-dimensional transistor devices. In some approaches, a method may include providing a plurality of fin structures formed from a substrate, the plurality of fin structures disposed subjacent to a hard mask layer, and directing angled ions at the plurality of fin structures. The angled ions may form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate, wherein the angled ions etch the plurality of fin structures to form a stack of isolated nanowires within the plurality of fin structures. The method may further include removing the hard mask layer, and forming a stopping layer over the stack of isolated nanowires.

Description

FIELD[0001]The present embodiments relate to semiconductor device structures, and more particularly, to structures and processing for three-dimensional transistor devices.BACKGROUND[0002]As semiconductor devices scale to smaller dimensions, the ability to harness device improvements with decreased size becomes more challenging. The synthesis of three-dimensional semiconductor transistors, such as fin type field effect transistors (finFET), gate-all-around transistor devices (GAA), or horizontal gate all around (HGAA) transistor devices involves challenging processing issues. HGAA structures are often referred to as a nanosheet device because the HGAA transistor formation entails formation of multilayers of nanometer-thick sheets of two different semiconductor materials grown in an epitaxial heterostructure. An example is a Si / SiGe superlattice stack composed of alternating silicon and silicon germanium alloy (SiGe) layers, and arranged in a vertical configuration having an overall f...

AI Technical Summary

Benefits of technology

This approach enables the formation of multiple nanowires without structural instability, simplifies integration, minimizes defect generation, and facilitates easier SiGe channel formation, resulting in improved device yield and performance.

Problems solved by technology

As semiconductor devices scale to smaller dimensions, the ability to harness device improvements with decreased size becomes more challenging.

The synthesis of three-dimensional semiconductor transistors, such as fin type field effect transistors (finFET), gate-all-around transistor devices (GAA), or horizontal gate all around (HGAA) transistor devices involves challenging processing issues.

These known approaches entail several drawbacks, including limits on the number of nanowires possible.

A larger number of nanowires requires a high fin aspect ratio, which may result in an unstable structure unstable.

Another drawback is the difficulty forming an inner spacer module, which does not exist in conventional finFET flows.

Another drawback is defect generation of strained Si nano-wire grown on SiGe during Si / SiGe supper lattice formation, which results in a low device yield.

Another drawback is the difficulty performing Si / SiGe intermixing with hot He implantation for STI densification.

Another drawback is the difficulty making SiGe channel for PFET.

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