Device structure and method for reducing silicide encroachment

Abstract

A semiconductor device having a novel spacer structure and method of fabrication. The present invention describes a semiconductor device which has an electrode with a first thickness. A silicide layer having a second thickness is formed on the electrode. A sidewall spacer which is formed adjacent to the electrode has a height which is greater than the sum of the thickness of the electrode and the thickness of the silicide layer.

Description

1. Field of the InventionThe present invention relates to the field of semiconductor device fabrication, and more specifically to a method and structure for reducing silicide encroachment in an integrated circuit.2. Discussion of Related ArtToday integrated circuits are made up of literally millions of active and passive devices such as transistors, capacitors, and resistors. In order to improve device performance, low resistance silicide layers are generally formed on electrodes such as gate electrodes and on doped regions such as source / drain regions.For example, FIG. 1A is an illustration of a portion of a complementary metal oxide semiconductor (CMOS) integrated circuit. Integrated circuit 100 includes a PMOS transistor 102 and an NMOS transistor 104 separated by an isolation region 103. NMOS and PMOS transistor 102 and 104 each include a pair of source / drain regions 106, a polysilicon gate electrode 107, and a gate dielectric layer 101. Insulative sidewall spacers 108 are forme...

AI Technical Summary

Problems solved by technology

A problem with the above described process is that circuits fabricated with the process are vulnerable to short circuits due to silicide encroachment.

Silicide encroachment can also cause short circuits between source / drain regions of adjacent devices which are separated by planar isolation regions.

Unfortunately, however, by increasing the thickness of polysilicon gate 107, the ion implantation technique used to dope gate electrode 107 (typically the source / drain implantation) is unable to drive dopants sufficiently deep into the electrode 107 to provide a uniformly doped low conductivity gate electrode.

When the lower portion (portion near gate dielectric layer 101) of the gate electrode has no or reduced doping, the device has increased gate resistance which detrimentally affects the drive current.

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