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Semiconductor device and its manufacturing method

a technology of semiconductor devices and manufacturing methods, applied in semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve problems such as the inability to mount larger semiconductor chips

Inactive Publication Date: 2009-04-28
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This design enables the mounting of larger semiconductor chips while maintaining the same package size, enhancing bonding accuracy and reducing the risk of chip damage during resin injection, and improves the pulling strength of the leads.

Problems solved by technology

Accordingly, it becomes a problem that mounting of the larger semiconductor chip cannot be achieved without changing the package size.

Method used

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  • Semiconductor device and its manufacturing method
  • Semiconductor device and its manufacturing method
  • Semiconductor device and its manufacturing method

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0067]A semiconductor device according to a first embodiment shown in FIGS. 1 and 2 is a small semiconductor package, which is assembled using a lead frame shown in FIG. 7 and is a single-surface-molding resin sealing type in which a sealing portion 3 is formed on a single-surface side of a lead frame 1 by resin molding, and it is further a peripheral type in which mounted surfaces 1d of a plurality of leads 1a are exposed to and arranged on a peripheral portion of a rear surface 3a of the sealing portion 3, and, as an example of said semiconductor device, a QFN 5 is taken and will be described.

[0068]Therefore, each lead 1a of the QFN5 functions as both an inner lead embedded in the sealing portion 3 and an outer lead exposed to the peripheral portion of the rear surface 3a of the sealing portion 3.

[0069]Note that, in the QFN 5 shown in FIG. 2, a tab 1b, which is a chip mounting portion, is formed to have about half thickness of that of the lead 1a since its rear surface 11 is scrap...

second embodiment

[0118]In a second embodiment, a QFN 9 having substantially the same structure as the QFN 5 described in the first embodiment will be described.

[0119]FIG. 15 shows a QFN 9 having a small tab structure in which the tab 1b shown in FIG. 16 is formed smaller in size than the main surface 2b of the semiconductor chip 2 and a tab embedding structure in which a portion of the sealing portion 3 is disposed on a side of the rear surface 11 of the tab 1b, wherein there is shown a flow condition of a resin (sealing resin) at a time of assembly of the QFN 9. That is, when the chip size increases, it becomes difficult for the sealing resin to enter a region between a side surface of the tab 1b and each lead 1a on a side of the rear surface 2c of the semiconductor chip 2, in the QFN 9 of the second embodiment. However, in the QFN 9 of the second embodiment, as shown in FIG. 16, the rear surface 11 of the tab 1b is processed to become thin by half etching etc., so that the sealing resin is made to...

third embodiment

[0199]In a third embodiment, a structure for enhancing a heat-radiation property in a semiconductor device having a QFN structure will be described. That is, the QFN 5 described in the first embodiment is formed so that the length (M) between the inner ends 1h of the sealing-portion forming surfaces 1g of the leads 1a disposed to oppose to each other is longer than the length (L) between the inner ends 1h of the mounted surfaces 1d, that is, “the length (M)”>“the length (L)” is formed. Consequently, it is possible to expand the chip loading region surrounded by the inner end 1h of the sealing-portion forming surface 1g of each lead 1a and to increase the mountable chip size without changing the package size. However, in such a semiconductor device, as shown in FIGS. 39 and 41, the QFN 15 of the third embodiment is such that there is mounted the semiconductor chip 2 having such large size that the chip end approaches each lead 1a.

[0200]In this case, as the semiconductor chip 2 becom...

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Abstract

There are constituted by a tab (1b) on which a semiconductor chip (2) is mounted, a sealing portion (3) formed by resin-sealing the semiconductor chip (2), a plurality of leads (1a) each having a mounted surface (1d) exposed to a peripheral portion of a rear surface (3a) of the sealing portion (3) and a sealing-portion forming surface (1g) disposed on an opposite side thereto, and a wire (4) for connecting a pad (2a) of the semiconductor chip (2) and a lead (1a), wherein the length (M) between inner ends (1h) of the sealing-portion forming surfaces (1g) of the leads (1a) disposed so as to oppose to each other is formed to be larger than the length (L) between inner ends (1h) of the mounted surfaces (1d). Thereby, a chip mounting region surrounded by the inner end (1h) of the sealing-portion forming surface (1g) of each lead (1a) can be expanded and the size of the mountable chip is increased.

Description

TECHNICAL FILED OF THE INVENTION[0001]The present invention relates to a semiconductor manufacturing technique and particularly to a technique effectively applied to enlargement of the size of a chip to be mountable.BACKGROUND OF THE INVENTION[0002]As a semiconductor device intended to be downsized, a small semiconductor package slightly larger in size than a semiconductor chip, which is called a QFN (Quad Flat Non-leaded Package), has been developed and the semiconductor package, having such a structure that a plurality of leads to be external terminals are disposed on a peripheral portion of a rear face of a sealing portion formed by a resin mold, is called a peripheral type.[0003]In the QFN, since the respective leads are exposed to the rear face of the sealing portion, bonding regions between the respective leads and a sealing resin are very small, so that various devices for increasing a bonding strength between each lead and the sealing portion have been made.[0004]Note that t...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H01L21/00H01L23/02H01L21/56H01L23/31H01L23/495
CPCH01L21/565H01L23/49548H01L24/97H01L23/3107H01L2924/014H01L2224/32014H01L2224/48091H01L2224/48465H01L2224/49171H01L2224/97H01L2924/01002H01L2924/01003H01L2924/01004H01L2924/01015H01L2924/01027H01L2924/01029H01L2924/01033H01L2924/01047H01L2924/01057H01L2924/01077H01L2924/01078H01L2924/01079H01L2924/01082H01L2924/14H01L2224/48247H01L2924/12041H01L2224/45144H01L24/48H01L24/49H01L2924/01005H01L2924/01006H01L2224/85H01L2924/00014H01L2924/00H01L24/45H01L2224/05554H01L2924/10162H01L2924/181H01L2924/18301H01L2924/351H01L2224/05599H01L2924/00012H01L23/50
Inventor SHIMANUKI, YOSHIHIKOSUZUKI, YOSHIHIROTSUCHIYA, KOJI
Owner RENESAS ELECTRONICS CORP
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