Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device has a semiconductor substrate having an impurity-diffused region and a device isolation insulating film formed in the surficial portion thereof, a gate electrode formed on the semiconductor substrate, a contact formed on the gate electrode and connected to the gate electrode, and a protective film disposed between the semiconductor substrate and the gate electrode, below the connecting portion between the gate electrode and the contact, formed wider in width than the gate electrode in a sectional view taken along the direction of gate length of the gate electrode.

Description

[0001]This application is based on Japanese patent application No. 2006-212445 the content of which is incorporated hereinto by reference.BACKGROUND[0002]1. Technical Field[0003]The present invention relates to a semiconductor device and a method of manufacturing the same, and more specifically to a semiconductor device containing a gate electrode and a contact connected to the gate electrode.[0004]2. Related Art[0005]Japanese Laid-Open Patent Publication No. H5-48022 describes a configuration in which a common gate electrode is disposed as extending over a P-type diffusion region composing a P-channel MOS transistor and an N-type diffusion region composing an N-channel MOS transistor, wherein the gate electrode is widened in the portion thereof which falls between the P-type diffusion region and the N-type diffusion region, as compared with the portion thereof which falls on these diffusion regions, and a contact connecting the gate electrode and an interconnect formed on the upper...

AI Technical Summary

Benefits of technology

The present invention provides a semiconductor device and a method of manufacturing the same that protects the surface of the semiconductor substrate during the formation of contact holes and reduces the risk of etching the surface of the semiconductor substrate. This is achieved by using a protective film that is formed below the connecting portion of the contact and the gate electrode. This protective film helps to relax restrictions on the design basis, allowing improvement in the degree of integration and micronization of the semiconductor device.

Problems solved by technology

However, the conventional solution by widening the gate electrodes in the connecting portions of the gate electrodes and the contacts has inevitably resulted in restrictions on the design basis, adversely affecting improvement in the degree of integration and micronization.

H11-195704, if the contact is formed wider than the gate electrode, there is a danger that the surficial portion of the semiconductor device is etched when forming the contact hole.

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