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Method of manufacturing semiconductor device having side wall spacers

a manufacturing method and semiconductor technology, applied in the field of semiconductor device manufacturing methods, can solve problems such as surface damage of silicon substrates, and achieve the effect of good controllability

Inactive Publication Date: 2009-11-03
YAMAHA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach enhances the precision of etching end point detection, improves the yield of semiconductor devices by reducing over-etching, and allows for precise control of etching amounts, stabilizing the quality of semiconductor devices despite variations in film thickness and etching rates.

Problems solved by technology

If etching continues after the silicon oxide film is etched, or in some cases, after the gate insulating film under the silicon oxide film is etched and the silicon substrate is exposed, the surface of the silicon substrate is damaged.

Method used

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  • Method of manufacturing semiconductor device having side wall spacers
  • Method of manufacturing semiconductor device having side wall spacers
  • Method of manufacturing semiconductor device having side wall spacers

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Embodiment Construction

[0022]Prior to describing embodiments, research made by the present inventor will be described.

[0023]According to the research made by the present inventor, it has been found that stability of detecting an etching end point is poor if an etching end point detecting method of monitoring an emission spectrum intensity of etching byproducts such as CO is adopted in a side wall spacer forming process of a method of manufacturing a MOS LSI containing a plurality of types of transistors having different gate insulting film thickness.

[0024]FIGS. 9A and 9B illustrate a side wall spacer forming method according to the research made by the present inventor. In a process shown in FIG. 9A, an isolation film (field insulating film) 2 made of a silicon oxide film and having element openings (active regions) 2a and 2b is formed in a surface layer of a semiconductor substrate 1 made of silicon, by local oxidation of silicon (LOCOS). A gate oxide film 3a made of a silicon oxide film having a thickne...

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Abstract

Gate insulating films 12A and 12B of different thickness are formed in element openings 16a and 16b in the isolation film 16 of a wafer 10. The gate insulating film 12B is the thinnest gate insulating film. A dummy insulating film having the same thickness as the thinnest gate insulating film 12B is formed in wafer periphery area WP. Gate electrodes 20A and 20B are formed on the gate insulating films 12A and 12B, and thereafter an insulating film is deposited on the wafer surface. The deposited insulating film is dry-etched to form side wall spacers 22a to 22d on side walls of the gate electrodes 20A and 20B. During dry etching, the time when the semiconductor surfaces are exposed in the element opening 16b and area WP is detected as an etching end point by a change in the emission spectrum intensity of etching byproducts.

Description

CROSS REFERENCE TO RELATED APPLICATION[0001]This application is based on and claims priority of Japanese Patent Application No. 2005-007286 filed on Jan. 14, 2005, the entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]A) Field of the Invention[0003]The present invention relates to a semiconductor device manufacture method, and more particularly to a method of manufacturing a semiconductor device having side wall spacers.[0004]B) Description of the Related Art[0005]Dry etching is performed by using etching gas in plasma state. By monitoring emission of etching byproducts, etching can be monitored. As an etching object is completely removed, emission by etching byproducts of the etching object extinguishes. Even if the etching object is not completely removed, if the area of the etching object is reduced, the emission intensity lowers.[0006]In most of manufacture processes for a MOS transistor, a gate electrode of polysilicon is formed on a...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H01L21/336
CPCH01L21/823814H01L21/823864H01L21/823857A61F5/003A61F5/0036A61B1/012
Inventor SUZUKI, TAMITO
Owner YAMAHA CORP