Electrostatic discharge circuit and method for reducing input capacitance of semiconductor chip including same
a technology of electromagnetic discharge circuit and semiconductor chip, which is applied in the field of electromagnetic discharge circuit and method for reducing input capacitance of semiconductor chip including same, can solve the problems of internal circuits being fatally damaged, the size of dram devices continues to decrease, and the semiconductor device can be destroyed by incidental contact with charged objects in the device's environment, etc., to achieve the effect of reducing the input capacitance of a semiconductor chip and reducing the input capacitance of a semiconductor
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Benefits of technology
Problems solved by technology
Method used
Image
Examples
Embodiment Construction
[0050]Exemplary embodiments of the invention are described below with reference to the corresponding drawings. These embodiments are presented as teaching examples. The actual scope of the invention is defined by the claims.
[0051]FIG. 4 is a graph illustrating a relationship between a junction capacitance Cj and a reverse bias voltage Vj in a semiconductor device. As seen in FIG. 4, an increase in reverse bias voltage Vj from 0V to 1V reduces junction capacitance Cj by about 0.1 pF. As reverse bias voltage Vj increases further, junction capacitance Cj decreases further.
[0052]The relationship between junction capacitance Cj and reverse bias voltage Vj can be expressed mathematically by the following equation (1):
Cj=Cjo / {(1+Vj / φ)^m}. (1)
[0053]In equation (1), the term Cjo denotes a junction capacitance in the absence of reverse bias voltage Vj, the term φ denotes a built-in voltage of a PN junction, and the term “m” is set to ½. As illustrated by equation (1), junction capacitance Cj...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 


