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Semiconductor apparatus

a technology of semiconductor devices and shielding elements, applied in electrical devices, semiconductor devices, semiconductor/solid-state device details, etc., can solve the problems of concentrating on output nmos and achieving protection nmos in parallel to output nmos not to achieve a sufficient protection

Inactive Publication Date: 2011-01-04
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This configuration enhances ESD capability by ensuring the protection transistor activates before the output NMOS, preventing breakdown and improving overall ESD protection without altering the design of active devices or increasing chip size.

Problems solved by technology

However, this type of semiconductor apparatus has the following problem.
Thus, upon application of ESD to the output terminal, the output NMOS is turned on earlier than the protection NMOS, and the flow of ESD current unfortunately concentrates on the output NMOS.
Hence, simply connecting the protection NMOS in parallel to the output NMOS does not achieve a sufficient protection effect.

Method used

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  • Semiconductor apparatus
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Examples

Experimental program
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first embodiment

[0020]Embodiments of the invention will now be described with reference to the drawings, starting with the invention.

[0021]FIG. 1 is a circuit diagram illustrating a semiconductor apparatus according to the present embodiment.

[0022]FIG. 2A is a cross-sectional view illustrating an output MOS, and FIG. 2B is a cross-sectional view illustrating a protection MOS.

[0023]FIG. 3 is a plan view illustrating this semiconductor apparatus.

[0024]As shown in FIG. 1, the semiconductor apparatus 1 according to the present embodiment includes an internal circuit 2. The internal circuit 2 provides the intended functions of the semiconductor apparatus 1, and is illustratively composed of a logic circuit for calculation and a memory for storing data. Furthermore, the semiconductor apparatus 1 includes a high-potential power supply line VDD and a low-potential power supply line VSS for supplying the internal circuit 2 with the potential of the high-potential and low-potential power supply, respectively...

second embodiment

[0073]Next, the invention is described.

[0074]FIG. 8 is a circuit diagram illustrating a semiconductor apparatus according to the present embodiment.

[0075]As shown in FIG. 8, the semiconductor apparatus 21 according to the present embodiment includes a protective P-channel MOSFET (hereinafter referred to as “protection PMOS”) 22. The source and the gate of the protection PMOS 22 are connected to the high-potential power supply line VDD, and its drain is connected to the output pad 6 through lines 23 and 11. More specifically, the line 11 extracted from the output pad 6 is split at the node N into the line 12 and the line 23. The line 12 is connected to the drain of the PMOS 4 and the drain of the NMOS 5, and the line 23 is connected to the drain of the protection PMOS 22. Thus the protection PMOS 22 is connected in parallel to the PMOS 4 between the output pad 6 and the high-potential power supply line VDD. By detouring the line 12, a resistance R is added between the node N and the ...

third embodiment

[0076]Next, the invention is described.

[0077]FIG. 9 is a circuit diagram illustrating a semiconductor apparatus according to the present embodiment.

[0078]As shown in FIG. 9, the semiconductor apparatus 31 according to the present embodiment includes both a protection NMOS 7 and a protection PMOS 22. The configuration and connection of the protection NMOS 7 and the protection PMOS 22 are the same as those of the above first or second embodiment. By detouring the line 12, resistances R are added between the node N and the NMOS 5 and between the node N and the PMOS 4, respectively. According to the present embodiment, both the NMOS 5 and the PMOS 4 can be protected from ESD. The configuration, operation, and effect of the present embodiment other than the foregoing are the same as those of the above first embodiment.

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PUM

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Abstract

A semiconductor apparatus includes an internal circuit, a CMOS composed of a P-channel MOS transistor with a source connected to a high-potential power supply line and a gate connected to the internal circuit, and an N-channel MOS transistor with a source connected to a low-potential power supply line and a gate connected to the internal circuit, an output terminal connected to a drain of the P-channel MOS transistor and a drain of the N-channel MOS transistor and a protection transistor with a source and a gate connected to one power supply line of the high-potential power supply line and the low-potential power supply line and a drain connected to the output terminal, a conductivity type of the protection transistor being the same as a conductivity type of one MOS transistor of the P-channel MOS transistor and the N-channel MOS transistor, the source of the one MOS transistor being connected to the one power supply line. Resistance of a current path extending from the output terminal through the one MOS transistor to the one power supply line has a value such that, when a voltage at which the protection transistor causes snapback is applied between the output terminal and the one power supply line, a current flowing through the current path is lower than a breakdown current of the one MOS transistor.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2007-149481, filed on Jun. 5, 2007; the entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]This invention relates to a semiconductor apparatus, and more particularly to a semiconductor apparatus including an output CMOS (complementary metal oxide semiconductor) circuit.[0004]2. Background Art[0005]As conventionally known in the art, in a semiconductor apparatus, a CMOS circuit can be provided as an output circuit for externally extracting an output signal of the internal circuit. The CMOS circuit comprises a P-channel MOSFET (metal oxide semiconductor field effect transistor) and an N-channel MOSFET. The source of the P-channel MOSFET is connected to the high-potential power supply line (VDD) of the semiconductor apparatus, and the source of the N-channe...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H01L21/70
CPCH01L27/0266H01L2924/0002H01L2924/00
Inventor SAI, HIDEAKI
Owner KK TOSHIBA