Method of multi-level storage in DRAM and apparatus thereof

Abstract

A method of processing data having one of four voltage levels stored in a DRAM cell is comprised of sensing whether or not the data voltage is above or below a voltage level midway between a highest and a lowest of the four levels, setting the voltage on a reference line higher than the lowest and lower than the next highest of the four levels in the event the data voltage is below the midway voltage level, and setting the voltage on the reference line higher than the second highest and lower than the highest of the four levels in the event the data voltage is above the midway point, and sensing whether the data voltage is higher or lower than the reference line, whereby which of the four levels the data occupies is read.

Description

[0001]This is a continuation of Reissue Application Ser. No. 08 / 595,020, filed Jan. 31, 1996, which is based on original U.S. Pat. No. 5,283,761 issued Feb. 1, 1994.FIELD OF THE INVENTION[0002]This invention relates to dynamic random access memory (DRAM) memories, and in particular to a method of storing a variable level signal in each cell of a DRAM for representing more than one bit in each cell.BACKGROUND TO THE INVENTION[0003]To store for example two bits in a DRAM cell, it must be able to store four different voltage levels. A problem with such cells, is that noise margins are reduced to one-third that of a one bit per cell DRAM, which is too low to withstand the occasional α-particle hit.[0004]A second problem with multi-bit storage cells relates to the method of sensing. No simple method of sensing has previously been designed, although attempts have been made to solve this problem, e.g. as described in the publication by M. Aoki et al, “A 16-Levels / Cell Dynamic Memory”, ISSC...

AI Technical Summary

Benefits of technology

[0011]In the present invention a method and circuit has been designed which substantially solves the above-identified problems. Only two sense amplifiers are required, which generate the sensing voltages at the time of sensing. In the present invention each bitline is split exactly in half, rather than into thirds, by use of a switch. The noise margins are relatively large, equivalent to that of a standard DRAM maintaining reliability, and the present design can be used as a standard one bit per cell DRAM as an alternative to a multiple bit per cell DRAM, which increases its universality, allows it to be used in present designs, and increases yield.

Problems solved by technology

A problem with such cells, is that noise margins are reduced to one-third that of a one bit per cell DRAM, which is too low to withstand the occasional α-particle hit.

A second problem with multi-bit storage cells relates to the method of sensing.

These levels are not self-compensated for offsets developed in the sensing operation, and this method suffers from poor signal margin.

Leakage characteristics of the DRAM cell were required to be very tightly controlled and even then, accurate sensing of the small voltage differences between levels becomes very difficult.

Another problem with this scheme was the length of time required to access: a single read cycle required 16 clocks for the read followed by 16 clocks for the restore.

A third problem is that the reference voltage is stored on a cell whose leakage does not track the leakage of the data cells, introducing another source of error into the circuit.

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