Method and system for displaying an analog image by a digital display device

Abstract

A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal.A system and method for displaying an analog source image by a digital display unit. A converter circuit generates a plurality of digital source image elements from an analog source image based upon a sampling clock signal synchronized with a time reference signal associated with the analog source image. A scaler unit receives the digital source image elements in accordance with a first clock signal, scales the source image elements independently in both vertical and horizontal directions to form destination image elements, and provides the destination image elements to the display unit in accordance with a second clock signal. The first clock signal and the second clock signal are arranged such that a source frame rate and a destination frame rate are substantially equal.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]More than one reissue application has been filed for the reissue of U.S. Pat. No. 6,320,574. The reissue applications are application Ser. No. 10 / 720,001(the present application), (Ser. No. 11 / 408,528) and (Ser. No. 11 / 408,669) all of which are divisional reissues of U.S. Pat. No. 6,320,574.<?insert-end id="INS-S-00002" ?>RELATED APPLICATIONS[0002]The present application is related to co-pending U.S. Patent Application entitled, “A Method and Apparatus for Upscaling an Image”, Filed Concurrently with the present application, Serial Number UNASSIGNED, Attorney Docket Number: PRDN-0001, and is incorporated in its entirety herewith.[0003]The present application is also related to and is a continuation of application Ser. No. 08 / 803,824 filed Feb. 24, 1997, now U.S. Pat. No. 5,796,392, entitled, “Method and Apparatus for Clock Recovery in a Digital Display Unit.”BACKGROUND OF THE INVENTION[0004]1. Field of the Invention[0005]The present...

AI Technical Summary

Benefits of technology

[0030]The clock recovery circuit includes a digital phase-locked loop (PLL). The bandwidth of the PLL can be instantaneously changed because of the digital implementation. In addition, the long term frequency and the temporary phase fluctuations are tracked using different control loops. As a result, considerable flexibility is available to a designer to track the time reference signal.

Problems solved by technology

In addition, the reference frequency can drift over a prolonged period of time due to, for example, temperature changes in the circuits generating the analog source image data.

Further, jitter may be present in both the reference signal and the clock signal generated by the analog PLL.

However, such a low bandwidth generally requires a capacitor having a large size, which may be hard to integrate into a relatively small-sized integrated circuits.

One problem with this approach is that noise is introduced into the analog PLL loop due to the external couplings.

Analog PLLs are generally sensitive to such noises, leading to instability in the PLL loop.

Without a low bandwidth in the loop, PLL 200 may be unable to track deviations in the reference signal closely, which may be unacceptable in some situations as explained below.

These deviations are usually more problematic for larger size display screens.

Such a skew between lines is generally perceptible for the human eye and the resulting display quality may be unacceptable.

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