Multi-phase locked loop for data recovery

Abstract

The present invention provides a multi-phase-locked loop without dead zone, which can reduce clock jitter and provide larger tolerance for data random jitter. It generates and output multiple sets of control signals (upk / dnk) via a multi-phase voltage controlled oscillator which generates a plurality of multi-phase clock signals for detecting the transition edge of data signal. Therefore, the phase error θe and the voltage Vd of the multi-phase-locked loop can be adjusted to be nearly linear according to the control signals. A multi-phase-locked loop without dead zone thus can be provided.

Description

FIELD OF THE INVENTION[0001]The present invention relates generally to a phase-locked loop for data recovery, and more particularly, to a multi-phase-locked loop that utilizes a multi-phase clock signal generated by a multi-phase voltage controlled oscillator (VCO) to detect received data.BACKGROUND OF THE INVENTION[0002]Due to the development of the network transmission technology as well as the demands in the installed base of computer networks, the network data transmission rate in hardware environment has been increased. Therefore, it becomes more and more important to recover data (clock signals) correctly.[0003]At present, while data (clock) recovery is to be performed, a phase-locked loop is often utilized. During the data recovery process, usually the received data could be correctly recovered (read) by using a phase detector to synchronize the received data and recover the clock. In other words, the phase detector plays a very important role whether the data could be correc...

AI Technical Summary

Benefits of technology

[0007]It is therefore an object of the present invention to provide a multi-phase-locked loop without dead zone, which can reduce clock jitter and provide higher tolerance for data random jitter.

[0008]Another object of the present invention is to provide a multi-phase-locked loop without static phase error.

[0009]The present invention is characterized by a multi-phase-locked loop which can generate a plurality of multi-phase clock signals by a multi-phase voltage controlled oscillater to detect the transition edge of the data signal data. Accordingly, multiple sets of control signals (upk / dnk) are generated. Therefore, phase error θe and voltage Vd of the multi-phase-locked loop can be adjusted to be nearly linear according to the output control signals. This prevents the multiphase-locked loop from having dead zone. Furthermore, the clock jitter can be reduced and provide greater tolerance for data random jitter.

[0016]The multi-phase clock signal (CKj+1) which is applied to the (j+1)th phase detection unit (Uj+1) and the multi-phase clock signal (CKj) which is applied to the jth phase detection unit (Uj). In accordance with the invention, the relation between the phase error θe and the voltage Vd of the phase-locked loop can be adjusted to be nearly linear by employing these control signals. Therefore, a phase-locked loop without dead zone can be derived, which can reduce clock jitter and enhance the tolerance for data random jitter.

Problems solved by technology

However, due to the above phenomenon, when the data signal data of the phase-locked loop has a phase lagging behind the clock signal CKvco, an obvious variation of Vd will be generated, which leads to clock jitter.

And, the tolerance for data random jitter becomes worse.

In other words, it is difficult to reduce the clock jitter for conventional phase-locked loops, large data random jitter is thus unaccepted.

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