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Common source EEPROM and flash memory

a technology of flash memory and common source, which is applied in the field of improved eeprom and flash memory, can solve the problems of difficult sensing circuitry to decide, difficult to correct the state of the selected memory transistor, and complicated design of the memory

Inactive Publication Date: 2009-11-17
MIND FUSION LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

"The present invention provides a nonvolatile memory array that includes a plurality of rows and columns of memory cell transistors. The sources of the memory cell transistors in each row are electrically coupled together, while the control gates of the memory cell transistors associated with a row are coupled to a wordline associated with that row. The drains of the memory cell transistors in a column of the array are coupled to a bitline associated with that column. A source transistor is associated with each row and has its source coupled to a common source line, its drain coupled to the sources of all memory cell transistors in that row, and a gate coupled to the wordline. The invention also provides an array of split-gate nonvolatile memory cell that includes a plurality of rows and columns of split-gate memory cell transistors. The sources of the split-gate memory cell transistors in each pair of adjacent rows are electrically coupled together, while the control gates of the memory cell transistors associated with a row are coupled to a wordline associated with that row. The drains of the memory cell transistors in a column of the array are coupled to a bitline associated with that column. A source transistor is associated with each row and has its source coupled to a common source line, its drain coupled to the sources of all memory cell transistors in that row, and a gate coupled to the wordline. The technical effects of the invention include improved performance and reliability of the nonvolatile memory array."

Problems solved by technology

Generation of these voltages complicates the design of the memories.
As a result an uncontrolled amount of current (hereinafter called leakage current) flows through the selected bitline and the common source, making the correct reading of the state of the selected memory transistor very difficult.
If this cell has been programmed to be normally on, it contributes current during reading and this make more difficult for the sensing circuitry to decide if the selected cell is on or off.
Another problem with a conventional array using a stacked gate cell and a common source is referred to as a “drain turn-on” problem.

Method used

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  • Common source EEPROM and flash memory
  • Common source EEPROM and flash memory
  • Common source EEPROM and flash memory

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second embodiment

[0060]Referring to FIG. 1, a memory byte 19 is separated by P-Wells PW0, PW1, . . . PWn with memory byte 19 selection being accomplished by using a CMOS inverter 18. Referring now to FIG. 3, memory byte 39 selection is accomplished using a multiple of source selection S0, . . . Sn replacing the need for the P-wells PW0, PW1, . . . PWn of FIG. 1. Accordingly, in a second embodiment, the multiple source selection nonvolatile memory cell array 30 of FIG. 3, is made of nonvolatile memory transistors 31. The multiple of source selection S0 . . . Sn are used for memory byte 39 or sector selection.

[0061]With the multiple of source selection S0 . . . Sn used for each memory byte 39 or sector selection, the entire array can be placed on a common well which does not have to be electrically isolated from the substrate.

[0062]FIG. 3 is an electrical schematic diagram of the multiple source selection nonvolatile memory cell array 30. Each nonvolatile memory transistors 31, has a source 32, a drai...

third embodiment

[0084]the present invention is shown in FIG. 5, the electrical schematic diagram of a split gate nonvolatile memory cell array 50. The split gate nonvolatile memory cell array 50 circuit depicted in FIG. 5 is similar to the nonvolatile memory cell array 10 circuit depicted in FIG. 1 with the differences note below.

[0085]Split gate nonvolatile memory cell array 50 is made of split gate nonvolatile memory transistors 51. Each split gate nonvolatile memory transistor 51, has a source 52, a drain 53, a floating gate 54, and a control gate 55.

[0086]Wordlines W0, W1, . . . W2n, W2n+1 overlap the floating gate 54 on two sides or one side only (as shown later in FIG. 8c, split gate memory cell layout). In the split gate nonvolatile memory transistor 51 the operation of the wordline over the diffusion area is called the memory select 69 or FIG. 6. Each of the wordlines W0, W1 . . . W2n, W2n+1 activates a row of control gates 55.

[0087]Source, S is used to select the N+ source diffusion common...

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Abstract

A nonvolatile memory array is arranged as a plurality of rows and columns of memory cell transistors. The sources of the memory cell transistors in each row of the array are electrically coupled together. The control gates of the memory cell transistors associated with a row in the array are coupled to a wordline associated with that row. The drains of the memory cell transistors in a column of the array are coupled to a bitline associated with that column. A source transistor is associated with each row and has its source coupled to a common source line, its drain coupled to the sources of all memory cell transistors in that row, and a gate coupled to the wordline. An array of split-gate nonvolatile memory cells is also disclosed.

Description

RELATED APPLICATIONS[0001]This application claims the benefit of U.S. Provisional Application No. 60 / 244,620, filed Oct. 30, 2000.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to semiconductor nonvolatile memories. More particularly, the present invention relates to an improved EEPROM and flash memories.[0004]2. The Prior Art[0005]Several types of nonvolatile memory cells have been used in commercial products for many years, ranging from EPROM to EEPROM and Flash memories. See, for example, “IEEE Standard Definitions and Characterization of Floating Gate Semiconductor Arrays” IEEE Std 1005-1998. The cited reference provides a good background of the various types of memory devices that have been produced and provide a list of the terms used in this disclosure.[0006]EPROM and Flash memories usually employ a single MOS transistor with two gates stacked on top of each other, the floating gate and the control gate, and the conductive state ...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G11C16/04H10B69/00
CPCG11C16/0416G11C16/0425H10B69/00
Inventor BERGEMONT, ALBERTSPADEA, GREGORIO
Owner MIND FUSION LLC