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Production method of semiconductor component and plug

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as component leakage current, abnormal electrical performance, and abnormal electrical connection

Inactive Publication Date: 2008-04-09
POWERCHIP SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this way, when contact plugs are subsequently formed in the contact openings 114 and 116, the formed contact plugs will be abnormally electrically connected to the exposed selection gate 106, causing leakage current or even abnormality of the device. electrical performance

Method used

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  • Production method of semiconductor component and plug
  • Production method of semiconductor component and plug
  • Production method of semiconductor component and plug

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0034] According to the present invention, a preferred embodiment is provided, applying the plug manufacturing method of the present invention to the process of trench flash memory. However, the present invention is not limited to be used only in the process of trench flash memory. The method of the present invention can be applied as long as a plug forms an electrical connection with one of the underlying adjacent components in the dielectric layer.

[0035] Figure 2A to Figure 2D Illustrated is a cross-sectional view of a manufacturing method of a plug according to a preferred embodiment of the present invention, which is formed in a dielectric layer and electrically connected with components of trench flash memory.

[0036] Please refer to Figure 2A, providing a substrate 300 with a trenched gate structure 302, wherein the trenched gate structure 302 may include a tunnel oxide layer (not shown), a floating gate (not shown), an intergate Electrical layer (not shown) and...

no. 2 example

[0045] According to the present invention, a preferred embodiment is provided, which applies the plug manufacturing method of the present invention to the interconnection process. However, the present invention is not limited to be used only in the interconnection process. The method of the present invention can be applied as long as a plug forms an electrical connection with one of the underlying adjacent components in the dielectric layer.

[0046] Figure 3A to Figure 3D Illustrated is a cross-sectional view of a method of manufacturing a dual damascene plug according to a preferred embodiment of the present invention, which is formed in a dielectric layer and electrically connected to an underlying conductive structure.

[0047] Please refer to Figure 3A , providing a substrate 400 with a conductive structure 420 . Next, a dielectric layer 404 is formed on the substrate 400 and covers the conductive structure 420 , wherein the material of the dielectric layer 404 is, f...

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Abstract

The method is designed for use in a substrate where a first conducting structure and a first dielectric layer are formed and comprises: forming a second conducting structure over a portion aside the first conducting structure; downsizing said second conducting structure to make the upper surface of said second conducting structure lower the upper surface of said first conducting structure; forming a second dielectric layer over the substrate; said second dielectric layer overlaps the first conducting structure and the second conducting structure; forming a via opening in the second dielectric layer; in the via opening the upper surface of the first conducting structure is exposed; finally forming a via plug in the via opening.

Description

technical field [0001] The invention relates to a semiconductor process method, in particular to an interconnection manufacturing method suitable for the semiconductor element process. Background technique [0002] With the integration level of integrated circuits getting higher and higher, semiconductor elements are developing toward miniaturization, so the dimensions of components, such as wire width, gate size, and plug size, must be reduced to increase their integration level. However, with the miniaturization of the components, the difficulty of the process is also greatly increased, and the requirement for dimensional precision is also increased. [0003] Existing photolithography and etching processes are used to form an exposed source / drain region or a gate above a storage element (such as a flash memory) or an interconnection line (such as a wire) in a dielectric layer. The contact window opening, or a via window opening that exposes the upper surface of the interc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/3213C23F1/32
Inventor 黄明山王炳尧陈大川
Owner POWERCHIP SEMICON CORP