Variable frequency synthesizer comprising a sigma-delta Modulator

Abstract

A variable frequency synthesizer comprising a sigma-delta modulator is provided. Such synthesizers provide an exact average frequency whereas the instantaneous frequencies are varied. The sigma-delta modulator comprises a plurality of accumulator stages being connected in cascade. At least one input value of an accumulator (51, 52, 53, 54) being part of the sigma-delta modulator has a second component, which is equal to an overflow signal (of1, of2, of3, of4) multiplied by a factor. This feedback reduces the maximum fluctuation of the instantaneous frequencies. Phase jitter generated by non-linearity of the phase detector, the charge pump and the VCO is therefore reduced.

Description

technical field [0001] The present invention generally relates to a frequency synthesizer, a frequency divider ratio controller and a method of operating a frequency divider ratio controller. Background technique [0002] A frequency synthesizer produces an output signal with a frequency that is an exact multiple of a reference frequency. The accuracy of the output signal frequency is determined by the accuracy and stability of the reference frequency. At the state of the art, frequency synthesizers are usually based on phase-locked loop (PLL) circuits. [0003] Generally, a PLL includes a phase detector circuit, an amplifier or charge pump, a filter circuit, and a voltage controlled oscillator. The phase detector circuit detects the phase difference of the two signals. One of these two signals is the reference signal. Another signal is generated in the PLL. The charge pump generates an analog signal with high current drive suitable for VCO control. The charge pump sig...

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Problems solved by technology

However, this frequency synthesizer is also very noisy at low frequencies, causing the aforementioned problems

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