The invention provides a method for extracting graphic features of the layout of a chip and a CMP (chemical mechanical polishing) simulation method. In the process of extracting the graphic features of the layout, an incremental partition method is adopted, firstly, the layout of the chip is partitioned into a plurality of grids, then any one grid is selected, the graphic feature of the selected grid is calculated, based on the grid, the size of the grid is gradually increased, the graphic feature of the grid after each increase in size is calculated, a method of weighted mean is adopted to calculate to obtain an equivalent grid graphic feature of the selected grid, then the same method is adopted to calculate to obtain the equivalent grid graphic feature of each of the rest grids of the layout of the chip, and all equivalent grid graphic features are used as the graphic features of the layout. According to the method, the incremental partition method is adopted as a correlative mechanism about proximity effects of all partitioned grids of the layout of the chip, the graphic proximity effects of different grids in the CMP process are taken into full consideration, the accurate prediction about the surface topography of the layout of the chip is realized, and the accuracy in simulation in the CMP process is improved.