Semiconductor memory device

Abstract

A substrate potential setting circuits are provided which control substrate potentials in units of columns of a memory cell array at least in data writing. Upon data writing, the potential of the substrate region of memory cell transistors on a selected column is changed to reduce the data holding characteristics (static noise margin) to ensure high-speed data writing to the memory cells. Data writing is performed at high speed without impairing stability of data retention.

Description

technical field [0001] The present invention relates to a semiconductor memory device, and more particularly to a structure of a memory cell array portion of a static type memory (SRAM (Static Random Access Memory)) that operates statically. More specifically, the present invention relates to a structure of an SRAM capable of stably writing and reading data with low current consumption. Background technique [0002] As a method of speeding up the operation speed of a MOS transistor, there is a method of reducing the absolute value of its threshold voltage. When the absolute value of the threshold voltage decreases, the leakage current can be increased, and the internal node can be charged and discharged at high speed. [0003] However, when the absolute value of the threshold voltage decreases, there is a problem in that the leakage current (subthreshold current) between the source and the drain in the off state increases, and the consumption current increases. Various pro...

AI Technical Summary

Problems solved by technology

As in the structure of Patent Document 2, at the beginning of the data writing operation, when the substrate potential is controlled to reduce the current driving capability of the drive transistor, the static noise margin is reduced, and it is not suitable for data writing.

However, even in the memory cells of the non-selected column of the selected row, the storage node is connected to the corresponding bit line, in the substrate control that reduces the current driving capability of the drive transistor in units of memory cell rows, the non-selected column of the selected row The static noise margin of the storage cells in the selected column is also reduced, and the data of the storage cells in the non-selected column is destroyed, which may cause malfunction

[0012] In addition, in any of the prior art, although the reduction of the consumption current during standby is considered, the reduction of the active current due to the charge and discharge of the bit line during operation is not considered.

[0013] In addition, in Patent Documents 3 to 5, only the layout of the memory cell array is considered, and circuit characteristics such as reduction of current consumption are not considered.

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