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Circuit with asynchronous/synchronous interface

A circuit and sub-circuit technology, applied in the field of asynchronously running processors, can solve problems such as waste of clock cycles

Inactive Publication Date: 2009-02-11
KONINKLIJKE PHILIPS ELECTRONICS NV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this can lead to wasted clock cycles when subcircuits run asynchronously to be able to supply data at high rates

Method used

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  • Circuit with asynchronous/synchronous interface
  • Circuit with asynchronous/synchronous interface
  • Circuit with asynchronous/synchronous interface

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0029]FIG. 1 shows a data processing circuit comprising an asynchronous instruction processor 10 , a peripheral handshake circuit 12 , an asynchronous peripheral 14 , an asynchronous-synchronous interface circuit 15 , a clock circuit 16 and a synchronous peripheral 17 . The asynchronous processor 10 has a peripheral handshake connection 11a, a read data input 11b, a write data / address data / control data output 11c, and a blocking / non-blocking select output 11d. Peripheral handshake circuit 12 couples peripheral handshake connection 11a of asynchronous processor 10 to connections 13, which are coupled to asynchronous peripheral 14 and asynchronous-synchronous interface circuit 15, respectively. Asynchronous peripheral 14 has a data output commonly coupled to data input 11 b of asynchronous processor 10 , and an address / data / control input coupled to output 11 c of asynchronous processor 10 . Although two asynchronous peripherals 14 are shown, it should be understood that there ma...

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Abstract

Data is communicated between an asynchronously operating circuit ( 10 ) and a clocked operating sub-circuit ( 16, 17 ). A data signal is supplied from the asynchronously operating sub-circuit ( 10 ) accompanied by a blocking / non blocking control signal. A request signal from the asynchronously operating sub-circuit ( 10 ) when the data signal and the control signal are being supplied. The data is stored in response to the request at least if the control signal supplied with the data has a first value. The request signal is routed through a path through handshake elements in a handshake circuit ( 20, 30,40 ) that is arranged to generate an acknowledge signal in response to the request signal to the asynchronously operating sub-circuit ( 10 ). The path through the handshake elements dependent on the control signal, so that the acknowledge signal is generated upon storing the data signal that accompanies the request at the output into the storage element when the control signal supplied with the data has the first value, and the acknowledge signal is generated upon detecting a clock cycle of the clocked operating sub-circuit wherein the clocked operating sub-circuit accepts the data that accompanies the request when the control signal has a second value.

Description

technical field [0001] The invention relates to a circuit having synchronously operating subcircuits and asynchronously operating subcircuits in communication with each other. More specifically, the present invention relates to an asynchronously operating processor interfaced to synchronously operating peripheral circuits. Background technique [0002] For communication between pairs of subcircuits, blocking or non-blocking interfaces are typically used. The blocking interface is used when a circuit that generates data must wait until the data is accepted before performing another operation. This is used, for example, when the effect of further operations depends on previous actions taken by the subcircuit receiving the data. When a non-blocking interface is used, the data-generating subcircuit performs further operations once it delivers the data to the storage unit for use by other subcircuits, without waiting for the other subcircuits. This is used, for example, when f...

Claims

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Application Information

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IPC IPC(8): G06F13/40
CPCG06F13/405
Inventor D·蒂默曼斯
Owner KONINKLIJKE PHILIPS ELECTRONICS NV
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