Memory device and manufacturing method of the same
A technology for storage devices and manufacturing methods, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve problems such as volatility limitation, impracticality, etc., to maintain product specifications and productivity, easy to use, and cheap. Effects of memory devices
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Embodiment approach 1
[0038] When a higher voltage than required for normal operation of the TFT is applied between the gate of the TFT formed on an insulating substrate and at least one of the two impurity regions (including the high-concentration impurity region), the channel region of the TFT be insulated. The operation is Figure 1A and 1B shown in Figure 1A and 1B are the cross-sectional views of the TFT before and after voltage application, respectively. For example, Figure 1A The TFT shown in has a semiconductor film 102 formed on an insulating substrate 101 , a gate insulating film 105 on the semiconductor film 102 , and a gate electrode 106 on the gate insulating film 105 . The semiconductor thin film 102 includes two high-concentration impurity regions 103 and a channel region 104 . Figure 1B The TFT after voltage application is shown. In this TFT, at least a channel region 104 of a semiconductor thin film 102 is modified, and an insulating region 108 is formed under a gate electro...
Embodiment approach 2
[0053] In the memory device of the present invention, a high-concentration impurity can be added over the entire surface of the semiconductor thin film of the TFT as a memory cell. On the contrary, impurities can be added to any part of the semiconductor film, and two wirings can be connected thereto; however, when impurity regions are formed arbitrarily, the element does not function as a transistor. Meanwhile, when a high-concentration impurity is added on the entire surface of the semiconductor film, all three terminals are insulated from each other by applying a voltage to at least one of the electrodes and the two wirings.
[0054]Described in this embodiment mode is an example in which one impurity region (in this embodiment mode, a high-concentration impurity region) is formed on a semiconductor film on an insulating substrate, and two wirings are connected to the semiconductor film, one of the electrodes Sandwiched in between. 3A and 3C are top views of elements havin...
Embodiment 1
[0066] In this example, refer to Figures 5A to 5E , Figures 6A to 6D as well as Figure 7A and 7B , specifically describing the fabrication method of a TFT on a glass substrate. The description is made with reference to cross-sectional views of N-channel TFTs and P-channel TFTs.
[0067] First, a peeling layer 501 is formed on a substrate 500 ( Figure 5A ). In this embodiment, an a-Si thin film (amorphous silicon film) having a thickness of 50 nm is deposited on a glass substrate (such as Corning Incorporated's product-1737 substrate) by low pressure CVD. For the substrate 500, a quartz substrate, a substrate made of an insulating material such as alumina, a silicon wafer substrate, a plastic substrate sufficiently heat-resistant to a heat treatment temperature in a subsequent step, and a glass substrate can be used . The lift-off layer 501 is preferably formed of silicon mainly containing such as polycrystalline silicon, single crystal silicon, and SAS (semi-amorpho...
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