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Method for forming double mosaic structure

A dual damascene structure and patterning technology, which is applied in the manufacture of electrical components, semiconductor/solid-state devices, circuits, etc., can solve the problems of thinning or interruption of metal connections, so as to improve the interruption of metal connections, prevent poisoning, and improve The effect of stability and reliability

Active Publication Date: 2009-04-29
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The invention provides a method for forming a dual damascene structure, which uses a barrier layer to prevent the photoresist from being poisoned, and improves the problem of thinning or interruption of metal connections in the existing dual damascene structure

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  • Method for forming double mosaic structure
  • Method for forming double mosaic structure
  • Method for forming double mosaic structure

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Embodiment Construction

[0046] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0047] The processing method of the present invention can be widely applied in many applications, and can utilize many suitable materials to make, and below is to illustrate by preferred embodiment, certainly the present invention is not limited to this specific embodiment, this field Common replacements known to those skilled in the art undoubtedly fall within the protection scope of the present invention.

[0048] Secondly, the present invention is described in detail using schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, which should not be used...

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Abstract

The invention discloses a method for forming a double-mosaic structure, which comprises the following steps: an underlay provided with at least one electric conduction zone on the surface is arranged, an etching stop layer is formed on the underlay, an interlayer dielectric layer is formed on the underlay, a photoresist is used to process the graph of a through-hole on the interlayer dielectric layer, the through-hole is formed by the etching process, a stopping layer is formed on the interlayer dielectric layer and the internal wall of the through-hole, the photoresist is used to conduct the graph processing on the stopping layer, the stopping layer and the interlayer dielectric layer are etched to form a groove; an electric conduction material is arranged in the groove and the through-hole, the electric conduction material is treated by a rubbing process to form the double-mosaic structure. The method can prevent the lining material from poisoning the photorsist in a lithography process, and can overcome the shortcoming of breaking of metal connection line in the double-inlaying process; the stability and reliability of the double-mosaic structure are improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a double damascene structure. Background technique [0002] As the production of integrated circuits develops towards ultra-large-scale integrated circuits (ULSI), the internal circuit density is getting larger and larger, and the number of components contained is increasing, making the surface of the wafer unable to provide enough area to make the required interconnection ( Interconnect). Therefore, in order to meet the increased demand for interconnection lines after component shrinkage, the design of multilayer metal interconnection lines with more than two layers has become a method that must be adopted in VLSI technology. Among them, after entering the 0.18 micron process technology, the dual damascene structure of copper and low dielectric constant (low k value, low dielectric constant) dielectric layer is adopted, because it can re...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
Inventor 王向东赵永红高俊涛
Owner SEMICON MFG INT (SHANGHAI) CORP