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Method for fabricating storage node contact hole of semiconductor device

A technology for storage nodes and contact holes, which is applied in semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., and can solve problems such as damage to the inside and top of storage node contact holes 15

Inactive Publication Date: 2009-06-24
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Also, when the remaining hard mask 13A is removed, the inside and top of the storage node contact hole 15 may be damaged.

Method used

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  • Method for fabricating storage node contact hole of semiconductor device
  • Method for fabricating storage node contact hole of semiconductor device
  • Method for fabricating storage node contact hole of semiconductor device

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0021] [twenty one] Figures 2A-2F is a cross-sectional view illustrating a method of manufacturing a storage node contact hole according to an embodiment of the present invention.

[0022] [22] If Figure 2A As shown, an intermediate insulating layer 22 is formed on a substrate 21 defined as a cell area and a peripheral area. The intermediate insulating layer 22 includes an oxide-based material. The oxide-based material may be one of a high density plasma oxide layer and a borophosphosilicate glass (BPSG) layer. The substrate 21 has been formed with transistors including word lines, sinker plugs and bit lines, and can be considered as a sinker plug. Therefore, it can be considered that the interlayer insulating layer 22 is a multilayer structure and the bit line BL is formed within the interlayer insulating layer 22 .

[0023] [23] A hard mask layer is formed on the intermediate insulating layer 22 . The hard mask layer includes an oxide layer, silicon nitride (Si 3 N ...

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PUM

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Abstract

A method for fabricating a storage node contact hole of a semiconductor device includes: forming an inter-layer insulation layer over a substrate; forming a hard mask over the inter-layer insulation layer; etching the inter-layer insulation layer to form a storage node contact hole; forming a passivation layer to fill the storage node contact hole; removing the hard mask with an etch rate of the hard mask faster than that of the inter-layer insulation layer; and removing the passivation layer.

Description

technical field [0001] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a storage node contact hole. Background technique [0002] As the design rules of dynamic random access memory (DRAM) devices have decreased, the thickness of photoresist layers used as masks to form contact holes has also decreased. Therefore, the photoresist layer is absent during the etching process. Recently, contact holes are formed using a hard mask to overcome this limitation. [0003] During the etching process of the storage node contact hole in the capacitor formation process of the DRAM, the polysilicon layer is mainly used to form the hard mask. A storage node contact plug connecting a landing plug formed in a lower portion of the storage node contact hole with the capacitor storage node fills the storage node contact hole. [0004] However, the polysilicon layer used as a hard mask causes mask alignment i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/311H10B12/00
CPCH01L21/76897H10B12/0335H10B12/482
Inventor 南基元
Owner SK HYNIX INC