Level conversion circuit

Abstract

The source of a p-channel MOSFET of a level conversion unit is connected to a supply terminal which receives supply voltage VDD. The drain is connected to an output node NO and the gate is connected to an input node I 2 . The source of a n-channel MOSFET is connected to an input node I 2 , the drain is connected to the output node NO and the gate is connected to the supply terminal which receives the supply voltage VDD. Input signals CLK 1 and CLK 2 change complementarily and difference of voltage between the high level and low level of the signals is smaller than difference between the supply voltage VDD and the ground voltage.

Description

field of invention [0001] The invention relates to level conversion technology, in particular to a level conversion circuit for converting the voltage amplitude of an input signal into another voltage amplitude. Background technique [0002] In recent years, as an integrated circuit using monolithic silicon, a chip called a silicon system is being developed in which a microprocessor or a memory and a logic circuit are mounted on the same chip. At the same time, technology development is underway to integrate various circuits into a single chip with as fine a design rule as possible. [0003] However, since each circuit is designed with different design rules, integration of circuits with different design rules is inevitable. As a result, a plurality of circuits operating with different power supply voltages are mixedly mounted in one chip, and voltage level conversion is required at their interfaces. In addition, since high-speed performance is originally required for the ...

AI Technical Summary

Problems solved by technology

When the level of the output potential Vout is inverted, a through current flows from the power supply terminal through the path of the P-channel MOSFET 801 and the n-channel MOSFET 803 or the path of the P-channel MOSFET 802 and the n-channel MOSFET 804 to the ground terminal. If the output potential Vout Level inversion takes time and increases power consumption

[0024] Additionally, for image 3 and Figure 4 The clamping circuits 821, 841 of the level shifting circuits 820, 840 are generally considered to have room for improvement in that they require a large configuration area.

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