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A forward error compensation and correction method and device for streamline analog/digital converter

An analog-to-digital converter, forward error technique

Inactive Publication Date: 2009-11-25
PEKING UNIV
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Problems solved by technology

Since such methods do not fundamentally solve the problems of power consumption and speed, the application prospects are limited

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  • A forward error compensation and correction method and device for streamline analog/digital converter
  • A forward error compensation and correction method and device for streamline analog/digital converter
  • A forward error compensation and correction method and device for streamline analog/digital converter

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Embodiment Construction

[0034] The present invention will be described in detail below through embodiments and in conjunction with the accompanying drawings.

[0035] Such as image 3 , 4 As shown, the present invention proposes a new error correction method for pipeline ADC——forward error compensation, the basic principle is as follows: when the sample-and-hold circuit in the pipeline stage is in the hold phase, the voltage error of its output point 5 will be reflected in The input virtual point 6 of the operational amplifier 4 is on.

[0036] The voltage value of the virtual point 6 can be approximated by the following method. During the sampling phase, the total charge on the input is:

[0037] Q s =(C F +C S )×VIN

[0038] C F : Holding capacitor of the sub-pipeline level

[0039] C S : The sampling capacitor of the sub-pipeline level

[0040] In the holding phase, the total charge input is:

[0041] Q h =C F (A×VX+VX)+C S VX

[0042] For 1-bit or 1.5-bit pipeline level, C is pref...

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Abstract

The present invention relates to a forward error compensation correction method and device of a pipelined analog-to-digital converter. The voltage error of the operational amplifier will be reflected on the input virtual point of its operational amplifier; the voltage error value of the input virtual point of the upper sub-pipeline stage operational amplifier is maintained and transmitted through a forward error compensation circuit, and compared with the input voltage of the lower sub-pipeline stage. The output voltage error of the upper sub-pipeline stage is accurately compensated; the sample-and-hold circuit for realizing forward error compensation and the pipeline stage use the same clock signal. The present invention adopts the pipelined ADC of the forward error compensation method and is supplemented with technologies such as multi-channel, time overlapping, can reduce the pressure of the baseband in the communication receiver system, can also solve the ADC resolution and speed of the software radio technology in the military equipment likewise on the bottleneck.

Description

technical field [0001] The invention relates to an error correction method for a pipelined analog-to-digital converter, in particular to a forward error compensation correction method and device for a pipelined analog-to-digital converter. Background technique [0002] With the development of electronic technology and computer technology, the use of digital signal systems to process analog signals has become more and more common. But in real life, most signals exist in the form of analog quantities. In the real world, the analog quantity in the form of an electrical signal converted by a sensor needs to be converted into a digital signal through an analog-to-digital converter (ADC) before it can be input into a digital system for processing and control. Therefore, the interface circuit ADC that converts analog quantities into digital quantities is a bridge between analog signals and digital signals, and is also the focus and bottleneck of electronic technology development. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/10
Inventor 樊亮李琛廖怀林黄如王阳元
Owner PEKING UNIV
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