Digital clock frequency multiplier

Abstract

A digital clock frequency doubler (100) for increasing incoming frequency of incoming clock signal includes a generator (102) for receiving incoming clock signal and high frequency digital signal. The generator (102) generates output clock signal by using periodicity counting (Nhf) of high frequency digital signal of incoming clock signal in one cycle dividing predetermined multiplication factor (MF). The output clock signal has predetermined output frequency.

Description

technical field [0001] The present application mainly relates to a frequency generator for generating digital signals, in particular to a digital clock frequency multiplier for increasing the frequency of an input clock signal. Background technique [0002] Clock multipliers are widely used in integrated circuits. Traditionally, a phase-locked loop (PLL) has been used as a clock multiplier to increase the frequency of the input clock signal. However, the PLL requires a lot of time and design effort to ensure its stability, consumes a large silicon area and often requires the use of external components, resulting in increased cost. In addition, because the PLL has a high lock time, the frequency of the input clock signal cannot be changed rapidly. In addition, PLLs are only suitable for processing input clock signals with a limited frequency and duty cycle range, and a single PLL has a limited multiplication range. [0003] From the foregoing observations, it is desirable ...

AI Technical Summary

Problems solved by technology

However, PLLs require a lot of time and design effort to ensure their stability, consume large silicon area and often require the use of external components, resulting in increased cost

Also, because the PLL has a high lock time, the frequency of the input clock signal cannot change rapidly

Furthermore, PLLs are only suitable for processing input clock signals with a limited frequency and duty cycle range, and a single PLL has a limited multiplication range

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