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Flattening method for flash memory device

A planarization method and technology of flash memory devices, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of reducing device reliability, fast erasing, time-consuming, etc., and prevent the existence of mobile ions or impurities , the effect of improving reliability

Inactive Publication Date: 2007-08-08
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, because the high-density plasma oxide layer 106 is formed by using an anisotropic deposition process, gaps (breach) 120 will be generated in the flash memory device near the periphery of the wafer, which will be processed in the subsequent process flow. After wet etching, an opening 130 can even be formed through the entire high-density plasma oxide layer 106
As a result, as shown in FIG. 1B , after successively forming the inter-gate dielectric layer 108 and the control gate (control gate) 110 with a relatively large area, a short circuit occurs because the control gate 110 is in contact with the substrate 100 ( short) problem
In addition, it is known that the high-density plasma oxide layer 106 is used as a dielectric layer, so mobile ions or impurities are likely to exist, thereby reducing the reliability of the device.
[0007] In addition, the above-mentioned known technology has other disadvantages. For example, when the flash memory device is in initial operation, the problem of fast-erase often occurs because the high-density plasma oxide layer 106 is used as the dielectric layer.
At present, in order to solve the above-mentioned shortcoming of fast erasing, it is usually to perform several program / erase operations before delivery, but this leads to time-consuming shortcomings

Method used

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  • Flattening method for flash memory device
  • Flattening method for flash memory device
  • Flattening method for flash memory device

Examples

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no. 1 example

[0034] 2A to 2E are flowcharts of planarization manufacturing of a flash memory device (FLASH memory device) according to a first embodiment of the present invention.

[0035] Please refer to FIG. 2A , a layer of tunnel oxide layer 202 is first formed on the substrate 200, and then a layer of floating gate 204 made of polysilicon is formed on the tunnel oxide layer 202, and a layer such as It is a capping layer 206 of a nitride layer, wherein the tunnel oxide layer 202 , the floating gate 204 and the capping layer 206 form a stacked structure 208 .

[0036] Then, referring to FIG. 2B , an oxide layer 210 is deposited on the substrate 200 to cover the stack structure 208 to prevent the substrate 200 from being exposed after the subsequent etching process, wherein the thickness of the oxide layer 210 is about 200 angstroms. Afterwards, an annealing treatment may also be performed to densify the oxide layer 210 , thereby improving the etch-resistant capability of the oxide layer ...

no. 2 example

[0041] 3A to 3D are flowcharts of planarization manufacturing of a flash memory device according to a second embodiment of the present invention.

[0042] Referring to FIG. 3A , a tunnel oxide layer 302 is formed on the substrate 300 with a thickness of about 70 angstroms to 100 angstroms. A floating gate 304 made of polysilicon is formed on the tunnel oxide layer 302 with a thickness of about 1000 angstroms. Next, an oxide layer 306 is formed on the floating gate 304 with a thickness of about 2000 angstroms. The tunnel oxide layer 302 , the floating gate 304 and the oxide layer 306 form a stack structure 308 .

[0043] Then, referring to FIG. 3B , a high-density plasma nitride layer (HDP nitride layer) 312 is formed on the substrate 300 to cover the stack structure 308 , wherein the thickness of the high-density plasma nitride layer 312 is thicker than that of the floating gate 304 And it is thinner than the stack structure 308, and its thickness is about 1500 angstroms to ...

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Abstract

The invention relates to flash memory flat method, which comprises the following steps: forming one layer of tunnel layer on base then forming one float electrode to form top cover layer; then if the top cover is of nitrogen layer and depositing one oxidation layer and forming one high intensity plasma glass; if the top cover is of oxidation layer then forming one intensive plasma nitrogen layer to cover the stack structure; then removing the plasma layer to expose top cover edge; then removing top layer and depositing layer.

Description

[0001] This application is a divisional application of the patent application with the application number "02142261.3", the application date is "August 28, 2002", and the invention name is "Planarization Method for Flash Memory Device". technical field [0002] The present invention relates to a manufacturing process of a flash memory device (FLASH memory device), and in particular to a planarization method of a flash memory device. Background technique [0003] At present, there is a planarization method for flat flash memory devices, which is a planarization method that does not use chemical mechanical polishing (CMP) manufacturing process. ), and then a floating gate is formed on the tunnel oxide layer, and a nitride layer is formed on the floating gate. Then, a high density plasma (HDP) oxide layer is formed on the substrate to cover the above devices. Next, part of the high density plasma oxide layer is removed to expose the top edge of the nitride layer. Subsequently...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/8247
Inventor 郑培仁
Owner MACRONIX INT CO LTD