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Computing group structure for superlong instruction word and instruction flow multidata stream fusion

A technology of ultra-long instruction word and single instruction stream, which is applied to the architecture with multiple processing units, concurrent instruction execution, general-purpose stored program computer, etc., which can solve the problems of reduced performance gain and increased difficulty, and achieve hardware efficiency High, improve throughput, avoid waste of storage bandwidth

Inactive Publication Date: 2007-08-22
NAT UNIV OF DEFENSE TECH
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Problems solved by technology

[0006] It can be seen that the current parallel development of computing-intensive applications such as multimedia and scientific computing is mainly based on independent instruction-level parallelism or data-level parallel development. In the case of continuous expansion of application scale and increasing complexity, parallelization using the above method The difficulty becomes larger, and the performance gain obtained is also decreasing

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  • Computing group structure for superlong instruction word and instruction flow multidata stream fusion
  • Computing group structure for superlong instruction word and instruction flow multidata stream fusion

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Embodiment Construction

[0020] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

[0021] Referring to Fig. 1, the computing group structure of the fusion of ultra-long instruction word and single instruction stream and multiple data streams of the present invention includes a main controller, data buffer, SIMD computing group and microcontroller. Among them, the main controller is responsible for the preparation of instructions and data, transfers the instructions that need to be executed by the SIMD computing group into the storage unit in the microcontroller, controls the start and pause of the SIMD computing group, transfers the required source operation data into the data buffer, and receives The final calculation result in the data buffer; the data buffer component receives the data transmitted from the main controller and stores it in a specific organization, providing the SIMD calculation group with the sourc...

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Abstract

This invention discloses a VLIW with single-instruction multiple data streams converging computing cluster structure, which includes the data buffer and microcontroller connected with main controller, and their connective computing cluster. The main controller are responsible for the instruction and data mobile, instruction loads in the microcontroller, data loads in the data buffer and receives their output. The data buffer receives main controller data, supplies operation data for computing cluster and receives its result, and outputs to the main controller. Microcontroller receives the VLIW sequence form main controller, decodes and broadcast to each processing unit for parallel execution. The computing group includes a number of same processing units with a number of dealing components respectively and the same instruction sequence, and the data is from different modules of data buffer.

Description

technical field [0001] The invention mainly relates to instruction processing technology in microprocessor design, especially applied to processors oriented to calculation-intensive calculations, and particularly refers to a calculation group structure in which ultra-long instruction words and single instruction stream and multiple data streams are fused. Background technique [0002] Instruction Level Parallelism (ILP for short) is the main way to develop parallelism in microprocessor design. Unrelated instructions can be executed in parallel to improve the efficiency of processor execution, such as superscalar technology and super long Instruction word technology (Very Long Instruction Word, referred to as VLIW). VLIW technology configures multiple functional components on the hardware, and they can execute instructions in parallel. The compiler is responsible for organizing the program into a sequence of super long instruction words. Each new instruction word contains mul...

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Application Information

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IPC IPC(8): G06F9/38G06F15/80
Inventor 邢座程杨学军张民选蒋江张承义马驰远李勇陈海燕高军李晋文衣晓飞张明穆长富阳柳曾献君倪晓强唐遇星
Owner NAT UNIV OF DEFENSE TECH
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