Computing group structure for superlong instruction word and instruction flow multidata stream fusion

A technology of ultra-long instruction word and single instruction stream, which is applied to the architecture with multiple processing units, concurrent instruction execution, general-purpose stored program computer, etc., which can solve the problems of reduced performance gain and increased difficulty, and achieve hardware efficiency High, improve throughput, avoid waste of storage bandwidth

Inactive Publication Date: 2007-08-22
NAT UNIV OF DEFENSE TECH
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Problems solved by technology

[0006] It can be seen that the current parallel development of computing-intensive applications such as multimedia and scientific computing is mainly based on independent instruction-level parallelism or data-level paralle

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  • Computing group structure for superlong instruction word and instruction flow multidata stream fusion
  • Computing group structure for superlong instruction word and instruction flow multidata stream fusion

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[0020] Hereinafter, the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments.

[0021] As shown in FIG. 1, the computing group structure of the present invention, which integrates ultra-long instruction words and single instruction stream and multiple data streams, includes a main controller, a data buffer, a SIMD computing group, and a microcontroller. The main controller is responsible for the preparation of instructions and data, transfers the instructions that need to be executed by the SIMD calculation group into the storage component in the microcontroller, controls the start and pause of the SIMD calculation group, and transfers the required source operation data into the data buffer and receives The final calculation result in the data buffer; the data buffer component receives the data from the main controller and stores it in a specific organization to provide the source operands required for the calcu...

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Abstract

This invention discloses a VLIW with single-instruction multiple data streams converging computing cluster structure, which includes the data buffer and microcontroller connected with main controller, and their connective computing cluster. The main controller are responsible for the instruction and data mobile, instruction loads in the microcontroller, data loads in the data buffer and receives their output. The data buffer receives main controller data, supplies operation data for computing cluster and receives its result, and outputs to the main controller. Microcontroller receives the VLIW sequence form main controller, decodes and broadcast to each processing unit for parallel execution. The computing group includes a number of same processing units with a number of dealing components respectively and the same instruction sequence, and the data is from different modules of data buffer.

Description

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Application Information

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Owner NAT UNIV OF DEFENSE TECH
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